Fujitsu Corporation

Fujitsu Microcomputer Systems Limited

Minoru Wano

Hiroyuki Miyazaki

Hiroyuki Yoshida

Yutaka Takinomi

Joji Murakami

Tomohiro Deguchi

IEEE 1394 bus interface circuit X comprises a physical layer LSI connected to an IEEE 1394 bus a data capture circuit X connected to the physical layer LSI through signal lines to capture data on the signal lines for data analysis, and a coupler (a plug or a socket) to be coupled to a coupler (a socket or a plug) to which a physical layer LSI of an IEEE 1394 bus interface is attached in actual use. With engaging the couplers and to each other, data transmitted between nodes and are captured by the data capture circuit X and analyzed in an IEEE 1394 bus analysis apparatus In another IEEE 1394 bus interface circuit, a link power status signal provided to the physical layer circuit from the link layer circuit is fixedly set low, whereby the physical layer circuit is made to function as a repeater, and data received by the physical layer circuit are captured by the link layer circuit and analyzed in the IEEE 1394 bus analysis apparatus.

Method and apparatus for IEEE 1394 bus analysis

A device for controlling a color video display which includes ladder resistor units having a plurality of taps; a clock signal generating unit for generating four-phase clock signals having the same frequency as the frequency of a sub-carrier from a clock signal having a frequency which is four times the frequency of the sub-carrier, and a color signal generating unit for receiving data corresponding to colors to be displayed and for generating color signals, by successively selecting taps of the ladder resistor units corresponding to the colors to be displayed, in synchronization with the four-phase clock signals. The generation of color signals having a precise phase angle relationships are ensured by this device.

Device for controlling a color video display

A pattern display signal generating apparatus comprises a memory for storing predetermined pattern data and for outputting even-numbered bits and odd-numbered bits of the pattern data in parallel when scanned, a timing generator for generating an address for scanning the memory and for generating first and second clock signal having a predetermined phase difference, a first shift register for shifting the odd-numbered bits and outputting the same in series in synchronization with the first clock signal, a second shift register for shifting the even-numbered bits and outputting the same in series in synchronization with the second clock signal, and a logical operation circuit for performing at least one predetermined logical operation between outputs of the first and second shift registers to generate a pattern display signal.

Growing community of inventors

Kanagawa, Japan

Minoru Wano