Nagase Co., Ltd.

Minoru Uwai

Yoichi Sato

Kanji Otsuka

Yutaka Akiyama

Toshiyuki Kouchi

Fumiaki Fujii

Kaoru Kobayashi

Masato Nishizawa

Tatsuya Nagasawa

A semiconductor device that writes, into respective memory spaces of a plurality of separate memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divided data are assigned respectively to the separate memories, and, by employing each divided data as an address, entry addresses corresponding to the divided data are written sequentially into memory spaces specified by memory addresses of the separate memories (first writing process). In this first writing process, if another entry address is already written in an accessed memory space, no entry address is written into that memory space. If an entry address corresponding to a single one of the plurality of pieces of divided data is successfully written into a memory space, the first writing process is ended. Second write processing to a verification memory may also be performed. Key data may be written to a backup memory when a whole collision occurs. The semiconductor device may also include multiple encoding circuits using different algorithms, and a narrowing unit to narrow down entry address candidates.

Writing method and semiconductor device including a search memory mat with write processing terminated when one piece of divided key data is successfully written

The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.

Semiconductor device and method of writing/reading entry address into/from semiconductor device

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Kanagawa, Japan

Minoru Uwai