Fujitsu Corporation

Fujitsu Semiconductor Limited

Cypress Semiconductor Corporation

Fujitsu Microelectronics Limited

Minoru Usui

Noriaki Ono

Hiroyuki Fujiyama

Hideaki Tomatsuri

Yasushi Nagano

In the display of an image including a fixed background image and a variation image of the background image, at least one of the amount of data to be held and the amount of work to be processed is reduced. A display control device acquires pixel description data including a combination of position information for specifying a position on a pixel array and address information for specifying an address in an image storage unit of image data which is displayed at the position specified by the position information. Furthermore, the display control device reads out the image data from the address of the image storage unit specified by the address information and specifies the position on the pixel array specified by the image description data to the display to input the read out image data.

Display control device to display image data

A microcomputer has: a CPU; memory; a direct memory access controller which controls access to the above memory without passing through the CPU; a plurality of peripheral resources, each having prescribed functions corresponding to a given real resource number, and issuing an access request to the direct memory access controller to perform data transfer with the memory; and, a resource conversion unit, which performs signal conversion between the direct memory access controller and the plurality of peripheral resources. A portion of the peripheral resources among the plurality of peripheral resources are associated with logical resource numbers of the direct memory access controller by the resource conversion unit.

Microcomputer with internal DMA

A stepping motor controller that alleviates the CPU burden of motor control tasks. An acceleration control starter initializes a pointer register with a given start angle address upon receipt of a control start signal. Duty cycles for different motor angles are previously calculated and stored in a duty cycle memory. A duty cycle selector looks up this memory to select specific duty cycles corresponding to the angle address held in the pointer register. The stepping motor is driven with pulse signals that a pulse generator produces according to the selected duty cycles. An angle address calculator adds a given address increment to the pointer register. A revolution detector detects one revolution of the stepping motor by comparing the angle address of the pointer register with an end angle address, which permits an acceleration constant calculator to change the angular increment upon detection of one revolution.

Apparatus, method, and system for controlling stepping motor

A noise filter, used for a digital signal, configuring an [N&#x2212;1]-stage filter by connecting the N-number of flip flops in series comprises a selection unit for outputting a filter output signal by selecting one of signals filtered by one to (N&#x2212;1) stages based on a selection signals; and a wave form check unit for making the selection unit change a selection thereby by changing a value of the selection signal based on a pulse width on the filter output signal which is output from the selection unit.

Noise filter and filtering method

A microcomputer comprises: a CPU which sequentially executes a program; an internal memory connected to the above CPU via an internal bus; a debug support unit, which monitors the internal state in response to an externally provided command; a monitor memory, which stores data stored in the internal memory, for being accessed by the debug support unit; and a monitor memory control unit, connected to the internal bus, which at a concurrent copy mode performs a control to concurrently write, to the monitor memory, data which is written to the internal memory in response to access from the internal bus, and at a monitor mode performs a control to read data in the monitor memory in response to access from the debug support unit.

Microcomputer capable of monitoring internal memory

A data processing device exchanges data between a memory and an external bus master. The memory is connected to the data processing device via a first bus so as to store data. The external bus master is connected to the data processing device via a second bus so as to process data. The data processing device comprises a bus-transmission control unit accessing the memory via the first bus in response to a request to access the memory made by the external bus master via the second bus.

Data processing device accessing a memory in response to a request made by an external bus master

The processor, upon fetching a sleep command, stops its own operation and outputs an internal power-down signal. The power-down control circuit outputs, upon receiving the internal power-down signal from the processor, a control signal to put a volatile semiconductor memory connected to the system bus into a self refresh mode. Thus, the processor can simply fetch the sleep command to put the semiconductor memory into the self refresh mode. Since system programs need not include any processing program for putting the semiconductor memory into the self refresh mode, the software processing can be prevented from being complicated. As a result, it is possible to reduce the burden on the program developers.

Memory control system

A memory control system employing at least one clock synchronous memory which is controlled by a memory control unit includes an interface circuit. The interface circuit functions as an output buffer synchronous with a clock. Thus, the interface circuit holds a memory control signal, which is output from the memory control unit for controlling the memory, and transmits the memory control signal to the memory in the predetermined time. In this configuration, access to the memory is made in consideration of the delay time required for a memory control signal to reach the memory via the interface circuit. Preferably, the presence or absence of the interface circuit for holding a memory control signal is determined based on an operation mode in which the memory control unit is established. Further proposed is a memory control method for controlling at least one clock synchronous memory which is implemented in the memory control system.

Memory control system and memory control method

Disclosed are a semiconductor device of which a block having a plurality of portions that operate based on a plurality of clocks can be designed and inspected easily, and a method of designing the semiconductor device. First and second clocks whose frequencies are mutually different are used to generate an enabling signal that is validated only during a short period including a transition edge of the second clock. The enabling signal and first clock are supplied to the second portion. The second portion synthesizes the enabling signal and first clock to substantially generate the second clock. Thus, the second portion is regarded as a portion that operates synchronously with the first clock.

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Kawasaki, Japan

Minoru Usui