Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Minoru Senda

Kiyohiro Furutani

Masaki Tsukude

Tadaaki Yamauchi

Hirotoshi Sato

Taku Ogura

Shigehiro Kuge

Satoshi Kawasaki

Hiroaki Nakai

Tadayuki Shimizu

Kiyoyasu Akai

Takeshi Agari

Shinichi Kobayashi

Shigeki Ohbayashi

Jun Setogawa

When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.

Semiconductor device for preventing erroneous write to memory cell in switching operational mode between normal mode and standby mode

The present invention provides a semiconductor device which comprises a plurality of memory cells which stores data therein based on threshold voltages thereof, a plurality of bit lines on which read signals based on the stored data of the memory cells appear respectively, a plurality of sense amplifiers which are respectively disposed corresponding to the bit lines and which respectively detect the read signals having appeared on the bit lines and output first and second signals respectively having logical levels different from one another from first and second nodes, based on the detected read signals, and a determination unit which determines, based on the first and second signals received from the first and second nodes of the sense amplifiers, whether the threshold voltages of the memory cells are normal.

Semiconductor device

In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of &#x2212;9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

Semiconductor device with pump circuit

A semiconductor device includes a boosting circuit for supplying a power supply voltage during a standby state of the semiconductor device. The boosting circuit includes a charge pump circuit and first and second detection circuits for detecting an output voltage of the charge pump circuit. The second detection circuit is operated by a DC current greater than that of the first detection circuit, and is activated by an output (Vdet) from the first detection circuit. The charge pump circuit is activated based on at least an output (Vdet) from the second detection circuit.

Semiconductor device having a boosting circuit to suppress current consumption

In operation, a charge pumping circuit supplies negative charges to an internal voltage line so as to reduce a negative internal voltage. A voltage dividing circuit produces a control voltage according to the difference between a first positive voltage externally applied to a first input terminal in the test mode and the internal voltage. A comparison circuit operates the charge pumping circuit according to the comparison result between a second positive voltage externally applied to a second input terminal in the test mode and the control voltage. The second positive voltage is set according to a target value of the negative internal voltage.

Semiconductor integrated circuit device including a negative power supply circuit

The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.

Semiconductor memory device having refreshing function

A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.

Semiconductor memory device having increased memory capacity while reducing mounting area and stand-by current

A voltage supply circuit has a resistive element, a p-channel MOS transistor, and n-channel MOS transistors. The resistive element and the p-channel MOS transistor are connected in parallel between a power source node and a node. The n-channel MOS transistors are connected in series between the node and the ground node. The voltage supply circuit supplies a threshold voltage of the n-channel MOS transistor to the node connected to a cell Vcc line of a memory cell in response to a test mode signal TE of the H level, and supplies an external source voltage in response to a test mode signal of the L level. In such a manner, a memory cell having an abnormal current in a standby mode can be detected by an operation test.

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Hyogo, Japan

Minoru Senda