Renesas Electronics Corporation

Mitsubishi Electric Corporation

Minoru Saeki

Daisuke Suzuki

Yuichiro Nariyoshi

There is a need to provide a central processing unit capable of improving the resistance to power analysis attack without changing programs, lowering clock frequencies, and greatly redesigning a central processing unit of the related art. In a central processing unit, an arithmetic unit is capable of performing arithmetic operation using data irrelevant to data stored in a register group. A control unit allows the arithmetic unit to perform arithmetic processing corresponding to an incorporated instruction. At this time, the control unit allows the arithmetic unit to perform arithmetic processing using the irrelevant data during a first one-clock cycle.

Central processing unit and arithmetic unit

There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.

Arithmetic unit and arithmetic processing method for operating with higher and lower clock frequencies

An electronic device that defends against an attack trying to identify confidential information from power consumption is provided without any circuit that performs a complementary operation to eliminate bias in power consumption. An elementary device Ais formed by a plurality of transistors-. The elementary device Areceives inputs signals x, x, a random number r, and a control signal en, and outputs z. The output z is obtained by XORing (x^r)&(x^r) with the random number r. After the state transitions of the input signal, x, x, and the random number r, are settled, the control signal en is used to output z. This makes the signal transition rate of the output z equal, thereby defending against an attack trying to identify confidential information from power consumption.

Electronic device and data processing device for implementing cryptographic algorithms

It is a purpose to evaluate a tamper resistance of an actual circuit with a high accuracy and at a high speed in an upstream process of a circuit design. A tamper resistance evaluating apparatus includes a signal change time counter unitfor counting the number of times a signal in a logic circuit changes, a power consumption calculation unitfor calculating a power consumption in the logic circuit based on the number of times a signal changes, which is counted by the signal change time counter unit, a leaked-information analysis unitfor analyzing information leaked from the logic circuit based on the power consumption in the logic circuit calculated by the power consumption calculation unit, a file databasefor storing a file used by a simulator, a simulation control information producing unitfor producing control information for controlling the logic simulator, a time sequence electric power information producing unitfor producing time sequence electric power information, in which the power consumptions calculated by the power consumption calculation unitare arranged in a time sequence, and a result displaying unitfor displaying the time sequence electric power information.

Electric power calculating apparatus, electric power calculating method, tamper resistance evaluating apparatus, and tamper resistance evaluating method

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Tokyo, Japan

Minoru Saeki