Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Minoru Okamoto

Hidetoshi Suzuki

Ryutaro Yamanaka

Kazuhiro Okabayashi

Hideyuki Kabuo

Kevin Mark Stone

Katsuhiko Ueda

Shinichi Marui

Masayuki Yamasaki

Toshihiro Ishikawa

Mitsuru Uesugi

Yukihiro Sasagawa

Nobuo Asano

Shirou Yoshioka

Yuji Sugisawa

Tetsuji Kishi

Toshio Sugimura

Takao Yoshida

Tatsuya Tetsukawa

Mikako Yasutome

Atsuhiro Mori

Mikio Sakakibara

A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.

Panel control device and panel control system

A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

Information contents download system

A plurality of logic element groups LEGto LEGrespectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEGand LEG, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element. The logic element groups LEGto LEGare therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

Reconfigurable semiconductor integrated circuit and processing assignment method for the same

A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.

Method of configuring information processing system and semiconductor integrated circuit

The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic deviceformed from programmable logical elements, there are provided first logical elementsand second logical elementshaving the same logic as the first logical elementsbut having an upper limit of operating speed designed to be lower than that of the first logical elements

Programmable logic device and method for designing the same

In a programmable cell included in a first region, configuration information is stored in a volatile memory, while in a programmable cell included in a second region, configuration information is stored in a non-volatile memory. Configuration information for a sub-process common to a plurality of processes is stored in the non-volatile memory.

Programmable device with structure for storing configuration information

A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.

Communications digital signal processor and digital signal processing method

An information processing method for coding a program to enable an information processing device having an instruction decoder having a reconfigurable circuit, comprises the steps of: simulating execution of the program to obtain a history of instructions executed; extracting a routine in which a number of types of codes used in at least a field among fields constituting an instruction is limited to a predetermined number or less, from the program based on the history; inserting an instruction for changing circuit configuration of the reconfigurable circuit at start and end of the routine; allocating codes so that number of times of change of bit values in a field in which the number of types of codes used are limited is reduced for the routine; and converting a program obtained in the step of inserting an instruction to codes according to the allocation for the routine.

Inserting decoder reconfiguration instruction for routine with limited number of instruction types recoded for reduced bit changes

Adequately assigning features provided by the system to processing units having different architectures incorporated in a system LSI. An analysis unit is provided for counting the number of conditional branch statements and the number of loop control statements, the number of nestings of the conditional branch statements and the number of nestings of the loop control statements, and the number of functions required to generate the conditions of the conditional branch statements and the number of repetitions of loop control statements described in each function of a program describing system features in a high-level language.

System LSI design support apparatus and a system LSI design support method

A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register&#x2014;register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.

Processing unit and processing method

An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.

Information processing apparatus and information processing method

A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.

Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture

A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection circuit, connected to a digital circuit, for protecting the digital circuit from destruction caused by ESD therein by an influence of an input digital signal and a second electrostatic destruction protection circuit, connected to an analog circuit, for protecting the analog circuit from destruction caused by ESD therein by an influence of an input analog signal. A first grounding conductor connected to the first electrostatic destruction protection circuit and a second grounding conductor connected to the second electrostatic destruction protection circuit are connected to each other outside the semiconductor integrated circuit.

Semiconductor integrated circuit device including digital and analog circuits comprising electrostatic destruction protection circuits

In a circuit blockto be an object of power-off, voltage detecting circuitsandare disposed near power supply terminalsand, respectively, and voltage detecting circuitsandare disposed at given positions far from the terminalsand, respectively, on power linesandof two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuitagain, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuitstops the input of a reset signal to the circuit blockAccordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

Semiconductor integrated circuit and its reset method

An execution control instruction is applied to an information processor of the type processing instructions by pipelining to suppress the occurrence of branch hazard. The execution control instruction contains: a condition field for specifying an execution condition; and an instruction-specifying field for defining, in binary code, the number of instructions to be executed only conditionally. In response to the execution control instruction, a nullification controller decides, based on control flags provided from an arithmetic logic unit, whether or not the execution condition specified by the condition field is satisfied. And based on the outcome of this decision, the controller determines whether or not that number of instructions, which has been defined by the instruction-specifying field for instructions succeeding the execution control instruction, should be nullified. If the controller has determined that the specified number of succeeding instructions should be nullified since the execution condition is not met, then the controller asserts a nullification signal to be supplied to the arithmetic logic unit. In this manner, a large number of succeeding instructions are executable conditionally using an execution control instruction of a short word length.

Growing community of inventors

Osaka, Japan

Minoru Okamoto