Texas Instruments Corporation

Hitachi, Ltd.

Minoru Ohtsuka

Hideo Aoki

Yoshitaka Tadaki

Toshihiro Sekiguchi

Jun Murata

Keizo Kawakita

Toshiyuki Kaeriyama

Songsu Cho

Katsuo Yuhara

Michio Nishimura

Kazuhiko Saitoh

Michio Tanaka

Yuji Ezaki

Takashi Hayakawa

Masayuki Yasuda

Takafumi Tokunaga

Kiyomi Katsuyama

Toshikazu Kumai

Akihiko Konno

Kazutoshi Taira

Katsutoshi Matsunaga

Yoshimi Torii

A method for fabricating DRAMs each having a COB structure, and the semiconductor device formed by this method, are provided. In one embodiment, the word line and/or bit line is covered with an insulating film having a comparatively small etching rate. Contact holes are formed while being defined by those insulating films in self-alignment.

Method of manufacturing semiconductor device with increased focus margin

A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Method of forming a semiconductor device have a screen stacked cell

The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

Method for forming semiconductor integrated circuit device having a

Method of making a semiconductor device, wherein an etchant gas is employed to etch a contact hole through an insulation layer overlying a conduction layer as disposed on a substrate of semiconductor material such that a surface portion of the conduction layer is selectively exposed by the formation of the contact hole through the overlying insulation layer. Normally, the etchant gas as so employed will have a tendency to react with the underlying conduction layer so as to form reaction products on the selectively exposed surface portion of the conduction layer increasing the contact resistance thereof. The method involves flooding the etched contact hole immediately following its formation with a gaseous medium covering the area of the selectively exposed surface portion of the conduction layer, wherein the gaseous medium is capable of inhibiting the formation of reaction products on the selectively exposed surface portion of the conduction layer from the original etchant gas. The formation of resistance-increasing reaction products on the selectively exposed surface portion of the conduction layer is thereby suppressed such that an undesirable increase in contact resistance is avoided. In a specific aspect, the etchant gas is a fluorine-based gaseous plasma, and the reaction product-inhibiting gaseous medium is a nitrogen-containing plasma.

Method of manufacturing a semiconductor device including plasma

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Fussa, Japan

Minoru Ohtsuka