Mitsubishi Denki Kabushiki Kaisha

Minoru Noda

Noriyuki Tanino

Shinji Orisaka

An insulating film having a through hole aligned with an electrode on a first semiconductor element is formed on a first semiconductor substrate and a metal is disposed in the through hole. A second semiconductor element on a second semiconductor substrate is placed on the insulating film in such a way that an electrode of the second semiconductor element contacts the metal. Thus, a plurality of transistors having different performance characteristics and functions can be easily disposed adjacent to each other for improved integration.

Semiconductor integrated circuit including opposed substrates of

A field effect transistor having an asymmetric gate includes high dopant concentration source and drain regions. The drain region is shallower and of lower dopant concentration than the source region. The drain is spaced from the gate electrode. Therefore, an ideal FET having a reduced short channel effect and having a lower source resistance and high current drivability (gm) is obtained. When the drain region is produced by ion implantation through a film and the source region is produced by the implantation directly into the substrate, only the drain region is separated from the gate. When the insulating film on the source region is separated from the insulating film on the drain region, the insulating film on the source region is reliably selectively removed, whereby high controllability is obtained.

Method of making an asymmetrical MESFET having a single sidewall spacer

A semiconductor integrated circuit includes an interlayer insulating film in which vacancies are evenly scattered. In this structure, the effective dielectric constant of the insulating film is reduced so that capacitance between upper and lower wirings and capacitance between adjacent wirings are reduced, resulting in a high speed semiconductor device. In production, a main material of the insulating film mixed with particles of a different material is applied to a surface of a wafer where the insulating film is to be formed. Then, the main material is solidified and the particles are selectively etched with an etchant that etches the particles but does not etch the main material, resulting in an insulating film in which vacancies are uniformly distributed. In this way, an insulating film having a low effective dielectric constant is formed in a simple process, resulting in a high speed semiconductor device having a small capacitance between wirings.

Method for producing a semiconductor integrated circuit

Method of making field effect transistor

A field effect transistor includes a semi-insulating substrate, first conductivity type source and drain regions disposed in the substrate, a first conductivity type channel layer having a lower dopant concentration than the source and drain regions and disposed between and connecting the source and drain regions, and a second conductivity type buried region disposed in the substrate adjacent to and contacting the first conductivity type channel layer but not contacting the source and drain regions. The leakage current from the channel region is greatly reduced without increasing the parasitic gate capacitance.

Field effect transistor and manufacturing method therefor

Field effect transistor

A permeable base transistor includes a source region and a drain region confronting each other in a semi-insulating semiconductor layer, a gate electrode having a current penetrating aperture through which a channel current flows disposed between the source region and the drain region and the source and drain regions, and the gate electrode are disposed so that the channel current flows transverse to the thickness of the semi-insulating semiconductor layer.

Permeable base transistor with gate fingers

A method of making a field effect transistor includes forming an active layer in a semiconductor substrate, forming a gate material on a portion of the surface as an ion implantation mask, implanting dopant ions to form a source region, depositing a first mask over the source region and a portion of the gate material, and removing the unmasked gate material to define a gate electrode. A second mask is deposited adjacent the gate electrode opposite the source region, and dopant impurities are implanted to form a drain region using the mask. The source and drain regions are asymmetrically doped and the gate electrode is asymmetrically disposed relative to the source and drain regions in the self-aligning process.

Method of making asymmetrical field effect transistor

A production method of a semiconductor device includes a first process for producing a gate electrode pattern of double layer structure on a semiconductor substrate, which gate electrode pattern comprises a first layer and a second upper heat-resistant material layers each having different etching property, a second process for plating a resist film on the entire surface of the substrate and etching the same to expose the top portion of the second upper heat-resistant material layer, a third process for removing the second upper heat-resistant material layer, a fourth process for hardening the surface of the resist and conducting over development of the resist, and a fifth process for plating a low resistance metal material on the entire surface of the substrate and removing the low resistance metal material together with the resist film by lift-off method, thereby to produce a gate electrode comprising the first lower heat-resistant material layer and a low resistance metal layer which is produced thereon, wherein the low resistance metal layer has a larger width than that of the first lower heat-resistant material layer.

Production method for a semiconductor device

An integrated circuit includes a semi-insulating semiconductor substrate; a first conductivity type high dopant concentration buried layer produced in the semi-insulating substrate; second conductivity type high dopant concentration drain and source regions produced at the surface of the semi-insulating substrate; a gate electrode produced on the surface of the semi-insulating substrate at a position between the drain and source regions; a second conductivity type channel layer produced between the drain and source regions; and a first conductivity type low dopant concentration region produced only below the second conductivity type channel layer between the second conductivity type drain and source regions in the first conductivity type high dopant concentration region; the drain and source regions being completely surrounded by the first conductivity type high dopant concentration buried layer from the bottom and outer side surfaces thereof. Alternatively, a first conductivity type high dopant concentration buried layer is provided only below and at outer side surfaces of the drain layer and a first conductivity type low dopant concentration buried layer is provided below the channel layer and the source region and at the outer side surface of the source region.

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Itami, Japan

Minoru Noda