Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Minoru Nagata

Koji Horie

Kenichi Hirashiki

Norio Hagiwara

Tsutomu Nakashima

A digital isolator includes: an edge detection circuit configured to output a first detection signal and a second detection signal; a driving buffer circuit configured to output a first edge signal and a second edge signal; an isolation element configured to output a first edge signal and a second edge signal; a receiving inverter circuit configured to output a first reception signal and a second reception signal; a latch circuit configured to latch data based on the pulse of the first received signal and the pulse of the second received signal, and to output an output signal to an output terminal according to the data; a switch circuit configured to switch a state of conduction between the reference potential and the first output and a state of conduction between the reference potential and the second output; and a control circuit configured to control a switching operation.

Digital isolator

A power supply circuitry includes a first circuitry, a second circuitry, a fourth circuitry, and a fifth circuitry. The first circuitry outputs a first current based on a drive signal. The second circuitry generates a second current according to the first current. The fourth circuitry generates the drive signal based on a first voltage according to the first current. The fifth circuitry outputs a second voltage based on the first current and on the second current.

Power supply circuitry and radio communication apparatus

In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.

Current mirror circuit

In one embodiment, a temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region, and a transistor which is supplied with the bias current. The bias circuit includes first to third transistors, a fourth transistor through which a first current flows, a fifth transistor, a sixth transistor through which a second current flows, and a control circuit having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current. The bias circuit generates a third current by adding the first current to the second current, and outputs the bias current that is the third current or a fourth current depending on the third current.

Temperature compensation circuit

A temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region in which a temperature is lower than a predetermined temperature, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region in which the temperature is equal to or greater than the predetermined temperature, and a transistor having a control terminal supplied with the bias current. The bias circuit includes a first current generating circuit configured to generate a first current increasing in proportion to the absolute temperature, a second current generating circuit configured to generate a second current that does not flow in the low-temperature region and flows in the high-temperature region, and a control circuit configured to control the second current and having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current, and is configured to generate a third current by adding the first current to the second current, and output the bias current depending on or equal to the third current.

A crystal oscillator which configures a voltage controlled oscillator having a variable oscillation frequency is also used as a crystal oscillator of an oscillator for generating a fixed frequency. Control input is integrated by an integrator, a phase of a frequency-divided signal obtained by dividing a fixed clock by a frequency divider is controlled by the integrated value to vary a frequency. Every time a phase-shifting amount at the time becomes to correspond to one clock, a frequency division ratio at dividing the clock is changed from a predetermined frequency division ratio for one time of frequency division to absorb the phase shifting amount for one clock, thereby operating as a voltage controlled oscillator. Thus, the voltage controlled oscillator having the frequency accuracy of a fixed clock is realized.

Frequency switching method, voltage controlled oscillator using same and receiver for spread spectrum communication using same

An FM signal oscillator circuit includes a resonator having a graded- or abrupt-junction variable capacitance diode that is producible through standard IC manufacturing processes but causes an inconstant modulation level. The FM signal oscillator circuit, therefore, is provided with a function of maintaining a constant modulation level irrespective of oscillation frequencies. Namely, to maintain a constant modulation level without regard to oscillation frequencies that change depending on a control voltage applied to the variable capacitance diode, the FM signal oscillator circuit employs a variable gain amplifier whose gain changes in response to the control voltage. The variable gain amplifier amplifies a modulating signal, and the amplified modulating signal is superimposed onto the control voltage. The superimposed signal is applied to the variable capacitance diode, and a driver of the FM signal oscillator circuit provides an FM signal whose modulation level is constant irrespective of the control voltage that may vary. With this configuration, the FM signal oscillator circuit is producible as an integrated circuit through standard IC manufacturing processes at low cost.

FM signal oscillator circuit and modulation level control method

A first differential amplifier amplifies the differential signal component of the input signal supplied to input terminals. The differential component is then supplied to output terminals. The first differential amplifier comprises a first differential pair of transistors for producing a differential output current proportional to the input signal, and two load impedance elements connected to the outputs of the transistors of the first differential pair, for converting the output current to a voltage output. A current source is coupled to both load impedance elements. The in-phase component provided at the output terminals is detected by a detector circuit. A second differential amplifier detects the difference between the in-phase component and a reference value. This difference changes the output current of the current source, thereby controlling the in-phase component.

Growing community of inventors

Yokohama, Japan

Minoru Nagata