Nippon Gakki Seizo Kabushiki Kaisha

Ascii Corporation

Yamaha Corporation

Minoru Morimoto

Takatoshi Ishii

Takatoshi Okumura

Shigemitsu Yamaoka

Kazuhiko Nishi

Ryozo Yamashita

Yoshiji Yoshida

Mutsuhiro Omori

Hidefumi Terada

There is provided a method of controlling direct memory access for a digital signal-processing system. Direct memory access (DMA) instructions for executing data transfer by direct memory access between a data memory storing data and an external device are provided in a program, together with arithmetic processing instructions for executing arithmetic processing. The data transfer by the direct memory access is executed between the data memory and the external device according to each of the DMA instructions which has been decoded during execution of the program, upon decoding thereof. There is also provided a digital signal-processing system which causes data transfer by direct memory access to begin. An arithmetic operation device of the system arithmetically processes data read out from a data memory of the same under the control of decoded instructions of a program. The program contains DMA instructions for executing the data transfer by the direct memory access as well as arithmetic processing instructions. The data transfer by the direct memory access between an external device and the data memory is started when each of the DMA instructions is decoded during execution of the program.

Digital signal processor with on board program having arithmetic

A method of filling a polygonal region enables a polygon of any shape to be filled with pixels with a simple algorithm. A display memory area and a working area each having a plurality of addresses correponding to all the pixels on a display screen are provided. A minimum rectangular area including the polygon is determined in accordance with all the polygon vertices, and the minimum rectangular area within the working area is cleared. A straight line (or an edge) connecting each pair of adjoining vertices of the polygon is described to the display memory area with predetermined values. The edges are also described to the working area but in accordance with three rules. Under Rule 1, when a constituent dot of the edge is described to the corresponding address, the data in the address is inverted. Under Rule 2, a start constituent dot of each edge is described only when the edge to be described has an inclination different in polarity from the precedingly described edge. Under Rule 3, the constituent dot of each edge is described only when the constituent dot is shifted in the vertical direction. Then, the rectangular area in the working area is scanned to detect dots in the state of '1' for each scanning line and to number the detected dots. Finally, addresses of the display memory area corresponding to each interval from the odd-numbered detected dot to the even-numbered detected dot are filled with predetermined values.

Method of filling polygonal region in video display system

A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area. A reading circuit reads the display data in the first memory locations in accordance with the first address data, while a writing circuit writes the read display data into the second memory locations in accordance with the second address data. This video display control system further includes another reading circuit and an operation circuit. This reading circuit reads the display data in the second memory locations and feeds the read display data to the operation circuit which effects an operation such as a logical operation or a transparency processing on each pair of the display data read from the first and second memory locations.

Video display control system for moving display images

A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM. Through this second register, the memory accessing circuit performs a memory accessing operation such as a transfer of color code between the external device and the VRAM, whereby color painting on a display area such as a rectangular area, dot and a line can easily be achieved. The VDP further comprises an operation circuit for effecting a certain operation on a color code in the second register and a color code in the VRAM and generating a new color code in accordance with the operation result. The operation-related color change on a display area can be achieved by storing the new color code in a corresponding memory location of the VRAM.

Video display control system

A video display control system comprises a video display processor (VDP) which is capable of accessing to a video RAM (VRAM) at an extremely high-speed. The VRAM used in this system comprises first and second dynamic RAMs each having an address input terminal to which row address data and column address data are supplied, a row address strobe input terminal, a column address strobe input terminal, and a data input/output terminal. The row address data is latched at the leading edge of a row address strobe signal applied to the row address strobe input terminal, while the column address data is latched at the leading edge of a column address strobe signal applied to the column address strobe input terminal. An access to an address of each dynamic RAM is established when both of the row and column address data are latched. The VDP comprises a VRAM interface for controlling an access to the first and second dynamic RAMs which is connected to the RAMs through a common address bus. The VRAM interface first outputs row address data together with a row address strobe signal RAS and then outputs column address data together with two column address strobe signals CAS0 and CAS1 which are rendered active in sequence and supplied to the first and second dynamic RAMs, respectively.

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Hamamatsu, Japan

Minoru Morimoto