Matsushita Electric Industrial Co., Ltd.

Minoru Kubo

Katsuya Nozawa

Tohru Saitoh

Yoshihiko Kanzawa

Takeshi Takagi

Kiyoshi Ohnaka

Koichiro Yuki

Yuzaburo Ban

Isao Kidoguchi

Yoshihiro Hara

Akihiko Ishibashi

Akira Asai

Hideto Adachi

Takeshi Uenoyama

Akira Inoue

Takahiro Kawashima

Koji Katayama

Teruhito Ohnishi

Masakatsu Suzuki

Yoichi Sasai

Yasuhito Kumabuchi

Masahiko Hashimoto

Shinichi Yamamoto

Hiroyoshi Komobuchi

Gaku Sugahara

Satoshi Kamiyama

Kenji Toyoda

Michio Okajima

Nobuyuki Uemura

Yo Ichikawa

Tadashi Narusawa

Toshiya Yokogawa

Nobuo Aoi

Takashi Nishikawa

Mototsugu Ogura

Shigetaka Aoki

Akemi Kawaguchi

Kazuhiro Ohkawa

Masaya Manno

Mototsugu Morisaki

In a field effect transistor, an Si layer, an SiC (SiC) channel layer, a CN gate insulating filmmade of a carbon nitride layer (CN) and a gate electrodeare deposited in this order on an Si substrate. The thickness of the SiC channel layeris set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source regionand a drain regionare formed on opposite sides of the SiC channel layer, and a source electrodeand a drain electrodeare provided on the source regionand the drain region, respectively.

Semiconductor devices and method for manufacturing the same

A silicon oxide film, a Pt film, a Ti filmand a PZT filmare deposited in this order over a Si substrate. The Si substrateis placed in a chamberso that the PZT filmis irradiated with an EHF wave. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate

Semiconductor device and method for fabricating the same

The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layerincluding an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

Heterojunction bipolar transistor having reduced driving voltage requirements

A thermal cleaning of a substrate that has been subjected to wet cleaning is carried out under a high vacuum atmosphere to remove an oxide film remaining on the substrate. Thereafter, a thermal cleaning is carried out under a hydrogen atmosphere to remove contamination such as carbon or the like. At this time, the oxide film has already been removed and therefore contamination is effectively removed by a relatively low temperature and short duration thermal cleaning. Thus, problems such as the degradation of the profile of the impurity concentration in the impurity diffusion layer which has been formed over the substrate are prevented.

Method for cleaning substrate and method for producing semiconductor device

An SGelayer (where 0&#x3c;y&#x3c;1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and SiGelayers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the SGelayer can be suppressed. As a result, the Si/SiGeinterface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.

An Al film is formed on a cap wafer and the Al film is patterned into a ring-shaped film. Dry etching is performed by using the ring-shaped film as a mask to form a drum portion enclosing a recess portion to provide a vacuum dome. After forming a depth of cut into the substrate portion of the cap wafer, the cap wafer is placed on a main body wafer having an infrared area sensor formed thereon. Then, the ring-shaped film of the cap wafer and the ring-shaped film of the main body wafer are joined to each other by pressure bonding to form a ring-shaped joining portion.

Semiconductor-based encapsulated infrared sensor and electronic device

A Si substratewith a SiGeC crystal layerdeposited thereon is annealed to form an annealed SiGeC crystal layeron the Si substrate. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer, which is lattice-relieved and hardly has dislocations, and SiC microcrystalsdispersed in the matrix SiGeC crystal layer. A Si crystal layer is then deposited on the annealed SiGeC crystal layer, to form a strained Si crystal layerhardly having dislocations.

Method of forming a semiconductor wafer having a crystalline layer thereon containing silicon, germanium and carbon

A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

Method of forming a semiconductor device including simultaneously forming a single crystalline epitaxial layer and a polycrystalline or amorphous layer

Electronic device and method for manufacturing the same

A multi-layer filmis formed by stacking a SiGeClayer (0&#x2266;x1&#x3c;1 and 0&#x3c;y1&#x3c;1) having a small Ge mole fraction, e.g., a SiGeClayer, and a SiGeClayer (0&#x3c;x2&#x2266;1 and 0&#x2266;y2&#x3c;1) (where x1&#x3c;x2 and y1&#x3e;y2) having a high Ge mole fraction, e.g., a SiGelayer. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

Semiconductor crystal film and method for preparation thereof

In a field effect transistor, an Si layer, an SiC (SiC) channel layer, a CN gate insulating film made of a carbon nitride layer (CN) and a gate electrode are deposited in this order on an Si substrate. The thickness of the SiC channel layer is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region and a drain region are formed on opposite sides of the SiC channel layer, and a source electrode and a drain electrode are provided on the source region and the drain region, respectively.

A semiconductor layer of a graded SiGe-HDTMOS is constructed of an upper Si film , an Si buffer layer , an Si Ge film and an Si cap layer . The region between a source region and drain region of the semiconductor layer includes a high concentration n-type Si body region and an n Si region , an Si cap region and an SiGe channel region . A Ge composition ratio x of the Si Ge film is made to increase from the Si buffer layer to the Si cap layer . For the p-type HDTMOS, the electron current component of the substrate current decreases.

Semiconductor device

The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

Heterojunction bipolar transistor

A lateral heterojunction bipolar transistor comprises a first semiconductor layer in a mesa configuration disposed on an insulating layer, a second semiconductor layer formed by epitaxial growth on the side surfaces of the first semiconductor layer and having a band gap different from that of the first semiconductor layer, and a third semiconductor layer formed by epitaxial growth on the side surfaces of the second semiconductor layer and having a band gap different from that of the second semiconductor layer. The first semiconductor layer serves as a collector of a first conductivity type. At least a part of the second semiconductor layer serves as an internal base layer of a second conductivity type. At least a part of the third semiconductor layer serves as an emitter operating region of the first conductivity type. The diffusion of an impurity is suppressed in the internal base formed by epitaxial growth.

Lateral heterojunction bipolar transistor and method of fabricating the same

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Mie, Japan

Minoru Kubo