Fujitsu Corporation

Minoru Koshino

Kazuyuki Shimizu

Shigeru Nagasawa

Akira Hattori

Keiichiro Uchida

Hidehiko Nishida

Terutaka Tateishi

Masanori Motegi

Takatoshi Muraoka

Masanori Takahashi

Yasuo Matsumoto

A storage-protection-check circuit includes a storage key corresponding to the unit area of a storage region, the storage key being stored in a key storage. The value of the access request key having an access request corresponding to the storage region is checked. When the access request key has a specified value, the storage region is accessed without reading the storage key out of the key storage.

Method and circuit for checking storage protection by pre-checking an

The present invention relates to an access request control apparatus and more specifically to an apparatus for determining priority between a plurality of access requests in a memory control apparatus which uses a pipeline. One of the access requests from a plurality of channel processing devices CHP's is selected by a first priority determination circuit. The selected CHP request, the requests from a plurality of central processing units and the request in the loop-back of the pipeline control circuit are considered for selection by a second priority determination circuit. In case a CHP request, selected by the first priority determination circuit, is not selected by the second priority determination circuit or selected but nullified in the course of the pipeline, the CHP request is returned to the first priority determination circuit. But, in this case, a higher priority is given to the CHP request in the first priority determination circuit. In addition, the priority algorithm in the second priority determination circuit considers the kinds of operations of each access request and highly efficient memory access control can be realized.

Access request control apparatus which reassigns higher priority to

A data processing system provides a diagnostic circuit having a scan-out function, that includes error checking. A scan-out address check code is generated by a sending unit and another scan-out address check code is generated by a receiving unit. The scan-out address check codes are compared in the sending unit, and an error in the scan-out operation can be detected.

Error detection of scan-out in a diagnostic circuit of a computer

This invention relates to a system for processing access requests issued from a plurality of access requesting units to a memory. In particular, in a storage system where the buffer storage BS and main storage MS are provided, access is first made to BS based on and access request and if the desired data is not found in BS, access is made to MS. When the desired data is not found in BS and access is then made to MS, acces to BS is carried out based on the next access request from the same access requesting unit in parallel with the access to MS by the first access request.

Access control processing system in computer system

A synchronizing circuit provides a plurality of signal transmission paths having different delay times in the line for transmitting signals. A pilot signal circuit has a pilot signal generator circuit which operates on the sending side, and a pilot signal is sent via one of the paths having a different delay time to a plurality of latch circuits on the receiving side. The output of each of the latch circuits is compared by a predicting circuit, so as to predict the phase difference between the clock signals of sending clock system and the receiving clock system. According to the result of this prediction, the signal transmission path having the optimum delay time is selected, so as to transmit the received signal that has been synchronized to the latch on the receiving side.

Synchronizing circuit

A memory access control system in a vector processing system comprises a memory unit, a memory device, address holding registers, a shift register and data buffer registers. The memory access control system distinguishes each vector data read out from the memory unit based upon the address holding registers by the output of the shift register. The shift register stores vector element numbers indicated by the memory device and transfers same to the data buffer registers. Each number from 0 to n-1, of a vector A composed of n elements a.sub.0, a.sub.1, a.sub.2, . . . a.sub.n-1, is a vector element number and each data, from a.sub.0 to a.sub.n-1, is vector element data.

Memory access control system in vector processing system

A system for controlling the addition of signed binary numbers represented with N bits, of the 2's complement notation, is disclosed which includes addend and augend sign control circuits, and an adder circuit comprising a carry save adder and a carry proper gate adder. The addend sign control circuit receives an operation command sign signal (B, --B, .vertline.B.vertline. or --.vertline.B.vertline.) for the addend, which designates the addend of the certain type (B, .vertline.B.vertline. or --.vertline.--B.vertline.) to be applied directly to the carry save adder and designates the addend of another type (--B, .vertline.--B.vertline. or --.vertline.B.vertline.) to be applied to the carry save adder through a 1's complementer. The augend sign control circuit functions similarly for the augend being applied to the carry save adder. A corrective number (0, 1 or 2) is applied to the adder circuit which corresponds to neither, one, or both the addend and augend being applied to the adder circuit through their respective 1's complementer.

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Yokohama, Japan

Minoru Koshino