Matsushita Electric Industrial Co., Ltd.

Minoru Itoh

Kenichi Tajika

Hiroki Tomoshige

In a clock delay adjusting method of a semiconductor integrated circuit device, a plurality of source points for adjusting a clock delay is provided to synchronize a value of the clock delay from each of the source points of each of hierarchical blocks in a semiconductor chip to a clock input circuit operating synchronously with a clock, according to circuit design conditions of the hierarchical blocks. Area terminals are provided in the source points, respectively. A clock input terminal of the semiconductor chip and each area terminal are connected through a clock line so as to be clock distributed over a hierarchical top. A clock delay between the hierarchical blocks is adjusted.

Clock delay adjusting method of semiconductor integrated circuit device and semiconductor integrated circuit device formed by the method

An input changing switch is provided at a preceding stage of a comparator that measures a DC offset of a D/A converter, and also a selective polarity inverting circuit is provided at a subsequent stage. A first compensation value is generated by a compensation value generating means and then stored in a register. Then, a second compensation value is generated by switching the input changing switch and the polarity inverting circuit and then stored in a register. Then, a third compensation value is calculated by averaging the first compensation value and the second compensation value by a compensation value calculating circuit. Then, the DC offset of the D/A converter is compensated by using this compensation value. Therefore, it enables to implement a precise DC offset compensation of the D/A converter by canceling the DC offset contained in the comparator itself employed in the DC offset compensation of the D/A converter.

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Shiga, Japan

Minoru Itoh