Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Minoru Inoshita

William A Shelly

Gerald N Winfrey

Robert J Baryla

Donald C Boothroyd

David S Edwards

Joseph L Ryan

Leonard G Trubisky

John P Stafford

Bruce E Flocken

Frederick E Kobs

Elisabeth Vanhove

Jiuyih Chang

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.

Information block transfer management in a multiprocessor computer

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for storing identification words identifying information blocks resident in the cache memory and including a status field indicative of the write permission authority the local CPU has on the block, an output buffer for storing the identification words of a block resident in the cache memory for which the CPU does not have and seeks write permission and for selectively sending identification words and an invalidate command onto the CPU bus, an input buffer for storing the identification words of all recent write permission requests in the group, a comparator for comparing the identification words in the output buffer with the identifications in the input buffer and control logic, responsive to the comparator sensing a compare condition (typically indicating a request by another CPU for write permission on the same block for which the local CPU has also requested write permission), for aborting the write permission request of the local CPU and establishing a retry process.

Multiprocessor computer system incorporating method and apparatus for

A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a 'siphon' operation to service the request of the other CPU.

Private cache miss and access management in a multiprocessor system with

A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.

Fault tolerant multiprocessor computer system

In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs.

Apparatus for detecting differences between double precision results

In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles. Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles. A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority. The peripheral subsystem having top priority may be wired either to relinquish the assigned DMA bus cycle after communicating with memory or 'hog' the assigned DMA bus cycle.

Direct memory access revolving priority apparatus

A cathode ray tube display terminal system includes a central processor subsystem and a number of certain peripheral subsystems all of which are coupled in common to a system bus. Apparatus in the central processor subsystem receives interrupt request signals from certain of the peripheral subsystems and on a predetermined priority basis modifies an address generated by the central processor subsystem in dependence upon which of the requesting certain peripheral subsystems has the highest priority. The modified address, called a vectored address points to a firmware subroutine stored in a memory subsystem which is also coupled to the system bus and which processes the interrupt from the highest priority cetain peripheral subsystem. Other peripheral subsystems coupled to the system bus generate a single interrupt signal which is also applied to the apparatus in the central processor system. The highest priority other peripheral subsystem generating the single interrupt signal responds to an interrupt acknowledge signal from the central processor subsystem by sending address signals to the apparatus which are used to modify the address generated by the central processing subsystem so as to produce the vectored address.

CRT display terminal priority interrupt apparatus for generating

A microprocessor controlled cathode ray tube display system has a plurality of peripheral devices all connected in common to a system bus. Apparatus in each peripheral device activates a single interrupt signal. A single acknowledge response signal to all the devices enables the interrupting device to place its address signals on the system bus thereby initiating a firmware routine for making the interrupting device operative with the system.

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Glendale, AZ, United States of America

Minoru Inoshita