Nec Corporation

Nec Electronics Corporation

Minoru Higuchi

Hitoshi Abiko

Ken Inoue

There is a room for improvement in conventional semiconductor devices in terms of reducing the chip area. A semiconductor devicecomprises an evaluation transistor(first characteristic evaluation device), an evaluation transistor (second characteristic evaluation device), measurement pads(first measurement pads) and measurement pads(second measurement pads). The measurement padand the measurement padare provided in different layers in the interconnect layer.

Semiconductor wafer and semiconductor device, and method for manufacturing same

A semiconductor device including an insulated gate field effect transistor (IGFET) has been disclosed. The IGFET may be formed in an element region defined by an element isolation region ( ) formed on a semiconductor substrate ( ). A covering portion ( ) may cover at least a portion of an end ( ) of the element region. Covering portion ( ) may be formed essentially of the same material as a side wall ( ) of a gate ( ) of the IGFET. A source/drain region ( ) may be formed using gate ( ) and covering portion ( ) as a mask. In this way, a distance between an intra-substrate high-concentration contour line ( ) and source/drain region ( ) in area of end ( ) of the element region may remain sufficient and an IGFET breakdown voltage may be improved.

Semiconductor device

A semiconductor device is herein disclosed which comprises a plurality of element regions formed on a first conductive type semiconductor substrate, element isolation regions for isolating the element regions from each other, and gate electrodes on parts of the element regions, the element regions being in contact with the element isolation regions at side surfaces of the element regions, wherein in the element region under each gate electrode, the concentration of a first conductive type impurity is high in an element region top surface edge area (in the vicinity of 66), and on the side surfaces of each element region, except the portions under the gate electrode, the concentration of the first conductive type impurity is equal to or lower than that of the first conductive type impurity in the body of the element region. According to the present invention, in the semiconductor device having a trench isolation, the formation of a parasitic channel at element region top surface edges under a gate electrode can be prevented and a leak current in an OFF state can be reduced without any increase in a junction capacitance which retards the driving velocity of elements and without any increase in a junction leak current.

Method for manufacturing a semiconductor device

There is provided a method for manufacturing a semiconductor device for forming a silicide layer of metal of high melting point, wherein the metal of high melting point is processed in sputtering under a condition in which no deterioration is produced by the sputtering apparatus. There is also provided a sputtering apparatus for manufacturing semiconductor device. In the method of the present invention, a high melting point metal is accumulated on a silicon substrate formed with a gate electrode of a semiconductor element to form a metallic film of high melting point, thereafter it is heat treated to form a silicide layer of the high melting point metal at an interface layer with the metallic film with high melting point, and in this case, the metallic film of high melting point is accumulated in sputtering by a magnetron sputtering device under a condition in which an electrical load amount Q reaching to the gate electrode is less than 5 C/cm,. In addition, the sputtering apparatus,has the collimator plate,including an electrical conductive material having many through-pass holes passed from the target toward the wafer between the target holder,and the wafer holder,while it is being connected to an earth terminal.

Sputtering apparatus for sputtering high melting point metal and method for manufacturing semiconductor device having high melting point metal

In a method of fabricating a semiconductor device by the use of a semiconductor substrate (,), boron ions (,) are implanted into the semiconductor substrate from a trench (,) which is formed to the semiconductor substrate. The trench is defined by a plurality of side surfaces and a bottom surface extending between the side surfaces. The boron ions are implanted through all of the side surfaces and the bottom surface. It is preferable that isolating material is filled into the trench to produce a trench isolation extending over a p-well (,) and a n-well (,).

Method of fabricating semiconductor device capable of providing MOSFET which is improved in a threshold voltage thereof

A semiconductor device is herein disclosed which comprises a plurality of element regions 50 formed on a first conductive type semiconductor substrate 60, element isolation regions 58 for isolating the element regions from each other, and gate electrodes 54 on parts of the element regions, the element regions being in contact with the element isolation regions at side surfaces 68 of the element regions, wherein in the element region under each gate electrode, the concentration of a first conductive type impurity is high in an element region top surface edge area (in the vicinity of 66), and on the side surfaces of each element region, except the portions under the gate electrode, the concentration of the first conductive type impurity is equal to or lower than that of the first conductive type impurity in the body of the element region. According to the present invention, in the semiconductor device having a trench isolation, the formation of a parasitic channel at element region top surface edges under a gate electrode can be prevented and a leak current in an OFF state can be reduced without any increase in a junction capacitance which retards the driving velocity of elements and without any increase in a junction leak current.

Growing community of inventors

Tokyo, Japan

Minoru Higuchi