Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Sanyo Electric Co., Ltd.

Minoru Akaishi

Satoshi Onai

Yoshiaki Sano

Hirotsugu Hata

Mitsuru Soma

Yoshimasa Amatatsu

Katsuya Okabe

Akira Yamane

Hiroshi Ishizeki

An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.

Semiconductor device and method of manufacturing the same

A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

Semiconductor device and manufacturing method of the same

In a semiconductor device according to the present invention, a plurality of opening regionstoare formed in an insulating film on a pad electrode. A metal layerformed on the pad electrodehas a plurality of concave portionstoformed therein by covering the opening regionsto. Moreover, in a peripheral portion at a bottom of each of the concave portionstoin the metal layer, the metal layerand a Cu plating layerreact with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode. Thus, a resistance value on the pad electrodeis reduced.

Semiconductor device and manufacturing method thereof

In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.

In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.

Growing community of inventors

Gunma, Japan

Minoru Akaishi