Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Electric Engineering Company, Limited

Minobu Yazawa

Shiro Hosotani

Natsuko Matsuo

Masatoshi Kimura

Kazuya Yamanaka

Toshio Kumamoto

Shinichi Nakagawa

Yasushi Wada

Hiroyuki Kouno

Yukinaga Imamura

A semiconductor device includes a delay amount measuring unit, multiple delay sections and a correction signal generating unit. The delay amount measuring unit for measures an actual delay amount corresponding to a specified delay amount by supplying a clock signal with a known period to multiple 1-ns-delay strings with a preassigned delay amount, and by detecting phase variations of the clock signal by the 1-ns-delay strings. The delay sections includes a delay string capable of freely adjusting a connection number of its delay elements. The correction signal generating unit generates a correction signal for enabling each of the delay sections to correct the connection number of the delay strings such that each delay section has a desired delay amount, in accordance with the actual delay amount corresponding to the specified delay amount and measured by the delay measuring unit.

Semiconductor device with delay correction function

A block to raster converting circuit which is adaptable to all formats with a single circuit is realized. Macro-block data is mapped into a frame memory ( ) on the basis of a particular format whose data size (X) in the horizontal direction provides a max condition. When writing, for each macro-block row (MBRi), the address of the first data in the initial macro-block (IMBi) is specified, on the basis of which address the column and row addresses are regularly switched according to the data array in the macro-block (MB). When reading, for each macro-block row (MBRi), the address of the initial data is specified, on the basis of which address the row address is switched every time data in each horizontal line in the macro-block row (MBRi) has been read and every time data at a turn of the column address in the frame memory ( ) has been read. The column address is sequentially switched.

Semiconductor integrated circuit for converting macro-block data into raster data which is adaptable to various formats

A decoder for converting packet data into raster data is provided. The packet data includes data about a picture-compressed video signal and data about a picture format including a picture rate. The decoder comprising a first processing means, second processing means and a storage means. The first processing means converts the packet data into intermediate data such that picture compression is eliminated from the picture-compressed video signal and outputs the intermediate data. The second processing means receives the intermediate data from the first processing means and processes the intermediate data to output raster data for one frame at a frame frequency. The storage means stores the intermediate data for processing the intermediate data in the second processing means. The second processing means writes the intermediate data into the storage means at a frequency related to the picture rate and reads the raster data for one frame from the storage means at the frequency equal to the frame frequency.

Displaying format converter for digitally encoded video signal data

The function of a line memory can be achieved only with one bit line. As word lines WL.sub.j-1 and WL.sub.j are activated in this order, data has already been read out before new data is written into memory cells MC.sub.j-1,i and MC.sub.j,1. More specifically, a writing process is performed on the same memory cell after a readout process, achieving delay operation as taught in a conventional technique. Further, as both operations of a tristate buffer 11 and a D latch 13 are controlled in accordance with the readout and the writing processes, one bit line serves both as a write bit line and a read bit line.

Line memory

Two input data X (7), Y (7), . . . , X (0), Y (0) are input to a plurality of full adders, and an overflow/underflow signal of each full adder is input to a full adder of a higher level. An overflow/underflow signal Co of the full adder of the most significant bit and data Y (7) are applied to an EXOR gate to obtain an exclusive OR. According to an output signal of the EXOR gate, an added output of each full adder or data Y (7) is selected by a selector, whereby a straight binary signal is output.

Overflow and underflow processing circuit of a binary adder

Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.

Dynamic memory

In an FIFO memory, a word line pointer (4) sequentially specifies word lines (8) in accordance with the first clock signal (CLK1) outputted from a clock generator (3). When the last pointer (5) outputs a last line access signal (PAS3) indicating that the last word line (8E) has been accessed, a control flag generator (2) detects that the last address has been accessed on the basis of the last line access signal (PAS3) and a clock signal (COS) in synchronization with the first clock (CLK1) and outputs a clock control signal (CCNT) in accordance with a timing of the detection. The clock generator 3 stops counting a reference clock signal (CLK0) in response to the clock control signal (CCNT). Thus, the access to a memory cell array of the FIFO memory is stopped in accordance with the number of effective pixels of inputted video signals, and thereby reduction in memory capacity and in power consumption can be achieved.

Sequential access memory

y memory blocks are connected in series. A row select signal is output to each memory block from a row address pointer corresponding to a plurality of memory circuits in one memory block. Similarly, a column select signal is output to each memory block from a column address pointer corresponding to a plurality of memory circuits in one memory block. Therefore, the same row and column select signals are applied to each memory block, whereby data is sequentially input/output for every memory block. Thus, the circuit complexity of the row and column address pointers can be reduced.

Sequential access memory that can have circuit area reduced

A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the Jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.

Counter device and method of operating the same

An A/D converter main body is formed in the form of an annulus with a wiring region set as its center, and a ladder resistor array for dividing an input reference voltage and an analog signal line for applying an input analog signal to each comparator in the A/D converter are formed in the form of an annulus with the wiring region set as a center. Wirings from terminals are once concentrated into the wiring region by an input/output line group and then distributed therefrom to circuit elements. Since the ladder resistor array is formed in a circular form, resistance values are less liable to change as compared to the case where the ladder resistor array is bent, resulting in a higher precision of reference voltages for comparison. Further, wiring lengths for control signals to be applied to the circuit elements are made equal, and there is no fear of line delays in the control signals.

Analog-to-digital converter of an annular configuration

A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.

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Hyogo, Japan

Minobu Yazawa