Matsushita Electric Industrial Co., Ltd.

Minobu Abe

Akio Nishimura

Tadashi Kobayashi

Shinichi Saeki

Kenji Nishimura

Toshiya Naka

Makoto Hirai

Yasushi Yoneda

Yorihiko Wakayama

Kiyoshi Maenobu

Noriyuki Hidaka

Jiro Minehisa

Kazu Segawa

Mitsuteru Kida

The present invention provides an image generation/composition apparatus and method capable of performing an anti-aliasing process or translucency process, and capable of obtaining a high quality image from shape data comprising coordinate values representing a three-dimensional shape without requiring an increase in cost.

Image generation apparatus, image generation method, image generation program recording medium, image composition apparatus, image composition method, and image composition program recording medium

An apparatus for parallel image generation has four geometric data buffers for storing four partial geometric data, respectively, and four image generators connected respectively to the four geometric data buffers. Each image generator generates a partial image data for every pixel in a frame. Further provided are four image mergers connected respectively to the four image generators. The four image mergers are also connected in series. An initial image generator for generating a background image is connected to the first image merger for merging the background image data and the partial image data from the first image generator. Each of the second to fourth image merger merges an output merged data from the previous image merger and the partial image data from the corresponding image generator. A timing control is connected to the four image mergers for controlling the merging timing in such a manner that the image merger carries out the merging operation of a pixel after the previous image merger has carried out the merging operation of the same pixel.

Parallel image generation from cumulative merging of partial geometric

Disclosed is an apparatus of synchronizing parallel processing among a plurality of processors including a plurality of synchronization units respectively corresponding to the plurality of processors and a control unit. The control unit and the synchronization units are connected in a loop. Each synchronization unit outputs a sync signal for informing that the synchronization unit has entered a wait state to an adjacent downstream unit. The control unit outputs a pulse for informing a completion of a synchronization among the processors to an uppermost-stream synchronization unit. The pulse is forwarded as far as an lowermost-stream synchronization unit. Each synchronization unit includes the following: a flag hold unit holding a flag indicating a state of a respective processor, a logical OR circuit ORing a sync signal sent from an adjacent upstream synchronization unit with a value of the flag and outputting an obtained value to an adjacent downstream synchronization unit as a sync signal, a detection unit detecting the pulse in a value outputted from the logical OR circuit, thereby initiating the flag hold unit, and an output unit outputting the value outputted from the logical OR circuit to a respective processor.

Apparatus for synchronizing parallel processing among a plurality of

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Hirakata, Japan

Minobu Abe