No. 24 Research Institute of China Electronics Technology Group Corporation

China Electronic Technology Corporation, 24th Research Institute

Chongqing Gigachip Technology Co. Ltd.

Minming Deng

Yuxin Wang

Tao Liu

Daiguo Xu

Guangbing Chen

Jian'an Wang

Ruzhang Li

Lu Liu

Xu Wang

Dongbing Fu

Gangyi Hu

Hanfu Shi

Jun Luo

Yan Wang

Shengdong Hu

Zhengping Zhang

Jianan Wang

Zhou Yu

Zicheng Xu

A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.

Multi-bit resolution sub-pipeline structure for measuring jump magnitude of transmission curve

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

Low-jitter frequency division clock clock circuit

Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M, M, Mand M, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M, M, Mand M, a second-stage common-source amplifier structure constituted by an NMOS transistor Mand a PMOS transistor M, a bias circuit structure constituted by NMOS transistors Mand Mand a PMOS transistor M, an amplifier compensation capacitor C, an amplifier load capacitor C, a reference current source Iref and a PMOS transistor Mthat provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor. Both input transistors and load transistors of a first-stage amplifier of the present invention adopt self-biased cascode structures, such that the output impedance and the DC gain of the first-stage amplifier are increased. Substrate voltages of the MOS transistors of the first-stage amplifier are provided by an amplifier bias circuit. Owing to a connection mode of the compensation capacitor C, a higher figure of merit is achieved.

Transconductance amplifier based on self-biased cascode structure

A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.

High-speed low-power-consumption trigger

The present invention provides a frequency-compensated transconductance amplifier, includes an input stage consisting of NMOS transistors Mand M, a first-stage active load consisting of PMOS transistors Mand M, a first-stage tail current source consisting of a constant current source Iss, a second-stage input transistor consisting of a PMOS transistor M, a second-stage constant current source consisting of an NMOS transistor M, a load capacitor consisting of a capacitor C, and a frequency compensation network formed by sequentially connecting a gain stage GAIN, a compensating resistor Rc and a compensating capacitor Cc in series.

Frequency-compensated transconductance amplifier

Growing community of inventors

Chongqing, China

Minming Deng