Sensors Unlimited

Hamilton Sundstrand Corporation

Minlong Lin

Joshua Lund

Robert Brubaker

Patrick Kuschak

John Liobe

A wavefront sensing pixel is provided. The wavefront sensing pixel includes a low-pass filter filtering a charge signal from a photodetector and outputting a control signal when low-frequency signals are detected in the charge signal, and a control device to control flow of the charge signal past the control device based on whether a low-frequency signal is detected in the charge signal. The wavefront sensing pixel further includes a low-frequency signal path that receives a flow of signals that flow past the control device, and a high-frequency signal path independent of the low-pass filter and the control device, the high-frequency signal path receiving high-frequency signals included in the charge signal.

Enhanced pixel for wavefront sensing

An imaging and pulse detection (IPD) pixel array includes a plurality of imaging pixels arranged in a plurality of rows and columns. Each imaging pixel includes a respective photodetector that outputs signals in response to incident light and input laser pulses. The signals include imaging signals that correspond to the incident light and pulse signals that correspond to the input laser pulses. The IPD array further includes an isolation circuit associated with each of the respective imaging pixels, each isolation circuit outputting filtered output pulse signals in response to receiving the signals from the associated imaging pixel, the filtered output pulse signals corresponding to the pulse signals. The IPD array further includes a single pulse detection circuit that toggles between a charged and uncharged state corresponding to a pulse being received from at least one of the isolation circuits.

Imaging pixel subarray with shared pulse detection

A pulse detector amplifier is disclosed. The pulse detector amplifier may have a detection switching leg that receives an input energy pulse. The pulse detector may have a mirror fast trigger including a trigger node and controlling a mirrored switching leg. The detection switching leg may trigger the trigger node in response to the input energy pulse. The pulse detector amplifier may also have a mirrored switching leg that controlled by the trigger node. The mirrored switching leg may control a voltage and/or current on the output node responsive to the input energy pulse. Thus, the pulse detector may generally include a cascode architecture, with a mirror fast trigger (which may include a FET) between the mirrored legs of the amplifier and enhancing the rapid triggering of the amplifier output. Thus the pulse detector may be power efficient, may have a small part count, and may be sensitive.

Pulse detection amplifier

An imaging pixel including a control device to control flow of a charge signal from a photodetector. The control device has a variable impedance that varies in response to frequency of an input signal, the control device being biased to permit signals to flow through the control device dependent on the frequency of signals being output by the photodetector. The imaging pixel further includes a low-frequency signal path that receives a flow of signals that flow through the control device, and a high-frequency signal path independent of the low-frequency signal path and the control device, the high-frequency signal path receiving high-frequency signals included in the charge signal.

Enhanced pixel for multiband sensing including a signal path to receive a flow of signals flowing through a control device

A leakage mitigation circuit is provided. The leakage mitigation circuit includes an inverter coupled to a storage node, wherein the storage node receives a signal output by an imaging pixel having a first voltage level to be stored. The inverter inverts the signal to a second voltage level. A single transistor coupled to the inverter and the storage node inverts the signal output by the inverter to the first level to hold the signal at the storage node to its original level. A self-biased device coupled to the inverter lowers current disturbance related to the storage node and increase threshold voltage at which fluctuation of the level of the signal at the storage node causes the signal to be inverted by the inverter.

Leakage mitigation at image storage node

An imaging pixel is provided. The imaging pixel includes a photodetector that outputs charge signals in response to incident light and laser pulses and a high-frequency path. A detector biasing circuit is further provided that biases high-frequency signals of the charge signals that are associated with the laser pulses to follow the high frequency path. The detector biasing circuit effectively filters low-frequency signal components of the charge signals from following the high-frequency path.

Pulse detection bandpass filter with gain stage

A pixel master-slave photodiode bias control amplifier system is disclosed. The pixel master-slave photodiode bias control amplifier system may include a master pixel and one or more slave pixels. The slave pixel(s) may be connected to a portion of the master pixel. In this manner, components may be shared between/among the master pixel and the slave pixel(s); thus, for example, optimizing the component count of the pixel master-slave photodiode bias control amplifier system and the size occupied by the pixel master-slave photodiode bias control amplifier system.

Pixel master-slave photodiode bias control amplifier

An imaging and pulse detection array includes: a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in the plurality of pixels and configured to detect a pulse on at least one of the pixels in the plurality of pixels, and each of the pixels in the plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein the imaging circuit and the pulse detection circuit include a shared portion.

Digital imaging and pulse detection array

A pixel cell includes a first integration capacitor, a second integration capacitor, a photo detector and a transistor. The first integration capacitor includes a first lead operatively coupled to the photo detector. The second integration capacitor includes a first lead. The transistor is operatively coupled between the leads of the first and second integration capacitors for enabling current flow between the photo detector and the second integration capacitor only once a threshold voltage is met on the first integration capacitor.

Integrating pixels and methods of operation

A pulse detecting imaging circuit includes a pixel array including multiple pixels arranged in at least one row and at least one column. The pixel array includes multiple row voltages and column voltages. Each of the row voltages is connected to each pixel in the corresponding row and each of the column voltages is connected to each pixel in the corresponding column. Each of said pixels includes an imaging circuit and a pulse detection circuit. An output of each pulse detection circuit is connected to a corresponding row voltage and a corresponding column voltage such that each pixel is configured to connect the corresponding row voltage and the corresponding column voltage to a ground or a known driven voltage in response to a pulse detection at the pixel.

Imaging circuit including frame asynchronous pulse detection

A circuit having a buffered direct injection (BDI) module is provided for image lag mitigation. The BDI module includes an optical detector coupled to a buffer. The buffer has a pixel amplifier which includes no more than two transistors. The BDI module includes a first current mirror coupled to the BDI module. The first current mirror generates a modulating current based on the output of the optical detector. The BDI module further includes a second current mirror coupled to the first current mirror. The second current mirror is configured to generate either an amplified or attenuated photocurrent operable to optimize an imaging time and scene brightness of the optical detector. The BDI module further includes a reset circuit, coupled to the second current mirror, and being configured to reset an integration capacitor which integrates an image signal based on the output of the optical detector.

Image lag mitigation for buffered direct injection readout with current mirror

Embodiments relate to systems and methods for image lag mitigation for a buffered direct injection readout circuit with current mirror. A photo detector device is coupled to a buffered direct injection (BDI) circuit, in which an operational amplifier and other elements communicate the output signal from the detector to subsequent stages. The BDI output is transmitted to a first current mirror, which can be implemented as a S&#xe4;ckinger current mirror. The first current mirror is coupled to a second current mirror, one of whose outputs is a fixed bias current. Image lag can be controlled by the fixed bias current, rather than the photocurrent produced directly by the optical detector. In aspects, the negative feedback provided by the first current mirror can increase the modulation of the second current mirror. This gain factor can reduce image lag to a significantly lower point than the lag experienced by known BDI-current-modulated readout circuitry without S&#xe4;ckinger current mirror.

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Plainsboro, NJ, United States of America

Minlong Lin