Texas Instruments Corporation

Minkle Eldho Paul

Sovan Ghosh

Amal Kumar Kundu

Laxmi Vivek Tripurari

Yujendra Mitikiri

Anukruti Chakraborty

Rahul Vijay Kulkarni

Seetharaman Janakiraman

Shridhar Atmaram More

An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

Analog-to-digital converter

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Kickback compensation for a capacitively driven comparator

An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.

Analog to digital (A/D) converter with internal diagnostic circuit

An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator coupled to the CDAC, and a successive approximation register (SAR) control circuit coupled to the CDAC and the comparator. The SAR control circuit is configured to successively select bits of a digital output value. The SAR control circuit is also configured to, after selection of the bits of the digital output value: maintain a state of first switches of the CDAC applied to select a most significant bit of the digital output value, and revert second switches of the CDAC applied to select bits of the digital output value having significance lower than the most significant bit to a state of the second switches prior to selection of the most significant bit.

Successive approximation register analog-to-digital converter

An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.

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Minkle Eldho Paul