Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Minjoon Park

Seunghoon Park

Jaehyun Lee

Dongchan Kim

Byunghoon Kang

Je-Woo Han

Junho Yoon

Keunhee Bai

Donguk Kim

Tae-Hwa Kim

Gyungjin Min

Chan-Won Kim

Kisoo Chang

Yunjong Jeong

Daehee Jang

Kuenhwan Kwak

Seongman Lee

Sangdong Kwon

Provided is a method of protecting an application from reverse engineering. The method includes registering, in an electronic device, a handler capable of being called as a preset fault is generated in the application, after the handler is registered, executing a protection code for generating the preset fault in the application, determining whether an environment where the application is executed is an abnormal environment, based on whether the handler has been called as the protection code is executed, and performing an operation for protecting the application, based on a result of the determination.

Electronic device for protecting application from abnormal environment and operating method thereof

Disclosed are an electrostatic chuck assembly and a substrate processing apparatus including the same. The substrate processing apparatus comprises a process chamber including an inner space therein, a gas supply unit supplying a process gas into the process chamber, a top electrode section in the process chamber and generating plasma from the process gas, and an electrostatic chuck assembly below the top electrode section in the process chamber. The electrostatic chuck assembly comprises an electrostatic chuck supporting a substrate, a focus ring surrounding an upper portion of the electrostatic chuck, an electrode ring below the focus ring and including a different material from the focus ring, and a brazed bonding layer brazing the focus ring and the electrode ring together, the brazed bonding layer being between the focus ring and the electrode ring.

Electrostatic chuck assembly and substrate processing apparatus including the same

Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1.

Methods of forming semiconductor devices using hard masks

A method of fabricating a semiconductor device is provided. The method may include forming an interlayer insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayer insulating layer, forming trenches in the first mask layer exposing the interlayer insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayer insulating layer may be greater than that of the key mask patterns with respect to the interlayer insulating layer.

Method of fabricating semiconductor devices

Growing community of inventors

Yongin-si, South Korea

Minjoon Park