Samsung Electronics Co., Ltd.

Hanon Systems

Makinarocks Co., Ltd.

Minjoo Lee

Wandon Kim

Hyunbae Lee

Sunyoung Noh

Jangeun Lee

Weonhong Kim

Rakhwan Kim

Eui Bok Lee

Minsik Kim

Moonkyun Song

Jongchan Shin

Ki Chul Park

Seungseok Ha

Euibok Lee

Joongjae Kim

Jeonghoon Lee

Soojung Choi

Seowoo Nam

Wonshick Ko

Je Yeol Lee

Dong Su Yoo

Kyeong Min Woo

Eunyoung Lee

Sungho Joo

A semiconductor device includes a substrate with an active region, a first interlayer insulating layer on the substrate, a first wiring in the first interlayer insulating layer that is electrically connected to the active region, an insulating pattern on the first interlayer insulating layer and that has a first opening exposing the first wiring, a double etch stop layer having lower and upper etch stop patterns on the insulating pattern and the first wiring, and including a second opening exposing a portion of the first wiring, a second interlayer insulating layer on the upper etch stop pattern and having a via hole connected to the second opening, the via hole having a rounded top corner region, a second wiring in the second interlayer insulating layer, and a via connecting the portion of the first wiring and the second wiring through the second opening and the via hole.

Semiconductor device with double etch stop layer and method of manufacturing the same

Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.

Semiconductor device

An integrated circuit device according may include a plurality of gate structures embedded in a substrate, a direct contact on the substrate between the plurality of gate structures, and a bit line electrode layer on the direct contact. The bit line electrode layer has a thickness of about 10 nm to 30 nm. The bit line electrode layer may include a molybdenum tungsten (MoW) alloy including molybdenum (Mo) a range of about 25 at % to about 75 at %.

Integrated circuit device

Disclosed is a method for controlling an energy management system that is performed by a computing device including at least one processor. The method may include acquiring a target temperature of one or more target points; and controlling one or more control variables using a reinforcement learning control model trained for a first condition regarding a state before a current temperature of the target points converges to the target temperature.

Method and apparatus for control energy management system based on reinforcement learning

A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.

Method of manufacturing semiconductor device

Growing community of inventors

Seoul, South Korea

Minjoo Lee