Samsung Electronics Co., Ltd.

Gwangju Institute of Science and Technology

Electronics and Telecommunications Research Institute

Minjae Lee

Beomjoon Kim

Youngseok Han

Kyeongkeun Kang

Jaerin Lee

Seungho Park

Seungbo Shim

Cheon Soo Kim

Dougyong Sung

Ja Yol Lee

Myungsun Choi

Yonghee Kim

Donghyeon Na

Minyoung Hur

Byunghun Han

Hyeongmo Kang

Jaehyun Kang

Junghyun Roh

Hyungyu Ju

Unho Cha

Sewon Lee

Junsoo Ko

Yang Azevedo Tavares

Minuk Heo

Dongju Lee

An apparatus and a method of correcting a mismatch of a time-interleaved analog-to-digital converter are provided. The apparatus may include: a time-interleaved analog-to-digital converter configured to receive a non-return-to-zero (NRZ) signal in a correction mode and generate a first output signal, and including a plurality of analog-to-digital converters; and a mismatch corrector configured to generate a second output signal by processing the first output signal of the time-interleaved analog-to-digital converter based on parameters, wherein the parameters may be generated based on the first output signal of the time-interleaved analog-to-digital converter in the correction mode, and a period of the NRZ signal may be different from a product of a sampling period of the time-interleaved analog-to-digital converter and a number of the plurality of analog-to-digital converters included in the time-interleaved analog-to-digital converter.

Apparatus and method for calibrating mismatches of time-interleaved analog-to-digital converter

A plasma etching method and a semiconductor device fabrication method, the plasma etching method including providing a source power having a first single pulse to an electrostatic chuck in order to generate a plasma on a substrate; providing a first bias power having a burst pulse different from the first single pulse to concentrate the plasma on the substrate; and providing a second bias power having a second single pulse the same as the first single pulse to accelerate the plasma toward the substrate.

Plasma etching method and semiconductor device fabrication method including the same

An analog-to-digital converter is provided. The analog-to-digital converter includes: a sample/hold circuit; a digital-to-analog converter; a plurality of comparison circuits; a control logic; and a digital register, wherein the plurality of comparison circuits include: a first comparison circuit configured to output a first comparison result signal in a first operation period; a second comparison circuit configured to, in a second operation period, calibrate an offset of a second comparison result signal based on a reference signal corresponding to the first comparison result signal among a plurality of reference signals and output the calibrated second comparison result signal; and a third comparison circuit configured to, in a third operation period, calibrate an offset of a third comparison result signal based on a reference signal corresponding to the calibrated second comparison result signal and output the calibrated third comparison result signal.

Analog-to-digital converter

An electronic device is provided. The electronic device includes an input interface and a processor that performs noise removal processing on an image input through the input interface, obtains first information on a first texture block among a plurality of first pixel blocks included in the input image, obtains second information on a second texture block among a plurality of second pixel blocks included in the noise-removed image, obtains third information on maximum energy amount among energy amount of each of the plurality of second pixel blocks, and identifies whether the input image is an upscaled image based on the first, second and third information.

Electronic device and control method thereof

A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop passing through the left-bottom corner region, a second conduction loop passing through the right-bottom corner region, a third conduction loop passing through the left-bottom corner region and the left-upper corner region, a fourth conduction loop passing through the right-bottom corner region and the right-upper corner region, and a shielding loop to shield electrical interference between the first through fourth conduction loops. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Defect detection structures, semiconductor devices including the same, and methods of detecting defects in semiconductor dies

An analog-to-digital converter, including a sample/hold circuit; a reference voltage driver; a digital-to-analog converter; a comparator; and a logic circuit, wherein the reference voltage driver includes: a first voltage supplier circuit configured to output an external supply voltage provided from outside of the analog-to-digital converter; a second voltage supplier circuit configured to output a sampled reference voltage that is obtained during a sampling phase based on control signals received from the logic circuit; and a switching driver configured to electrically connect the first voltage supplier circuit to the digital-to-analog converter during a first conversion phase after the sampling phase based on the control signals received from the logic circuit, and to electrically connect the second voltage supplier circuit to the digital-to-analog converter during a second conversion phase based on the control signals received from the logic circuit.

Disclosed is a display apparatus. The display apparatus obtains first characteristic information, which is provided according to a plurality of sections of content and corresponds to an image characteristic of a section to be displayed among the plurality of seconds, from a signal received in the signal receiver, obtains first image-quality setting information for setting image quality of the section based on the obtained first characteristic information, obtains second characteristic information corresponding to an image characteristic of a frame included in the section from the frame, obtains second image-quality setting information for setting image quality of the frame based on the obtained first image-quality setting information and the obtained second characteristic information, and controls the display to display an image of the frame, the image quality of the frame being set based on the obtained second image-quality setting information.

Display apparatus and control method thereof

Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.

Phase locked loop for reducing fractional spur noise

Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.

Phase locked loop and operating method thereof

Disclosed herein is a mixer. The mixer may include an MLO switching unit configured to include at least three MLO switches provided in odd numbers and configured to branch a signal from an input stage and to receive respective MLO signals and an LO switching unit configured to include pairs of LO switches connected in parallel to output sides of the MLO switches, wherein each of the pairs of LO switches corresponds to each of the MLO switches. Each of the pairs of LO switches is connected to the positive and negative intermediate frequency (IF) output sides so that the output sides of each of the pairs of LO switches alternately apply output signals to the positive and negative IF output sides when LO signals are sequentially input to each of the pairs of LO switches.

Growing community of inventors

Gwangju, South Korea

Minjae Lee