Samsung Electronics Co., Ltd.

Ulsan National Institute of Science and Technology

Harvard College

Seoul National University

Cornell University

The University of Chicago

Minhyun Lee

Hyeonjin Shin

Minsu Seol

Yeonchoo Cho

Changseok Lee

Haeryong Kim

Donhee Ham

Youngtek Oh

Hyeonsuk Shin

Minseok Yoo

Seokmo Hong

Houk Jang

Taein Kim

Kyung-Eun Byun

Seunggeol Nam

Gukhyon Yon

Junyoung Kwon

Henry Julian Hinton

Jinseong Heo

Seongjun Park

Keunwook Shin

Changhyun Kim

Jiwoong Park

Ho Won Jang

Kibum Kim

Saien Xie

Kyungyeol Ma

Renjing Xu

Dovran Amanov

Chengye Liu

Hyeyoung Kwon

A vertical NAND flash memory device and a method of manufacturing the same are provided. The vertical NAND flash memory device includes a charge trap layer arranged on an inner wall of a channel hole vertically formed on a substrate. The charge trap layer includes nanostructures distributed in a base. The nanostructures may include a material having a trap density of about 1×10cmto about 10×10cm, and the base may include a material having a conduction band offset (CBO) of about 0.5 eV to about 3.5 eV with respect to the material included in the nanostructures.

Vertical NAND flash memory device and method of manufacturing the same

Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

Semiconductor device including two-dimensional semiconductor material

Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

Wiring including graphene layer and method of manufacturing the same

Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

Field effect transistor including channels having a hollow closed cross-sectional structure and method of manufacturing the same

Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

Vertical nonvolatile memory device including memory cell string

A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.

Nonvolatile memory device and operating method of the same

Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

Field effect transistor including gate insulating layer formed of two-dimensional material

An image sensor includes a visible light sensor portion and an infrared sensor portion arranged on the visible light sensor portion. The visible light sensor portion includes a first sensor layer and a first signal wiring layer, wherein a plurality of visible light sensing elements are arrayed in the first sensor layer and the first signal wiring layer is configured to process a signal output from the first sensor layer. The infrared sensor portion includes a second sensor layer in which a plurality of infrared sensing elements are arrayed, and a second signal wiring layer configured to process a signal output from the second sensor layer. The infrared sensor portion and the visible light sensor portion form a single monolithic structure which is effective in obtaining high resolution.

Image sensors integrated with infrared sensors and electronic devices including the same

A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.

Nonvolatile memory device and apparatus including the same

An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

Interconnect structure and electronic apparatus including the same

Disclosed is a neural computer including an image sensor capable of controlling a photocurrent. The neural computer according to an embodiment includes a preprocessor configured to receive an image and generate a feature map for the received image; a flattening unit configured to transform the feature map generated by the preprocessor into tabular data to provide data output; and an image classifier configured to classify images received through the preprocessor by using the data output by the flattening unit as an input value. The preprocessor includes an optical signal processor configured to receive the image and generate the feature map.

Neural computer including image sensor capable of controlling photocurrent

A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

Boron nitride layer, apparatus including the same, and method of fabricating the boron nitride layer

Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

Two-dimensional material-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices

A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.

Transistor including two-dimensional (2D) channel

A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

Growing community of inventors

Suwon-si, South Korea

Minhyun Lee