Lg Electronics Inc.

Samsung Electronics Co., Ltd.

Korea Institute of Science and Technology

Nanofaentech Co., Ltd.

Trina Solar Co., Ltd.

Minho Choi

Seongeun Lee

Sungjin Kim

Jonghwan Kim

Se-Gon Roh

Youngbo Shim

Ilhyoung Jung

Jeongbeom Nam

Haejong Cho

Juhwan Yun

Jinah Kim

Younghyun Lee

Myungjun Shin

Haewook Ahn

Daehyun Kim

Sangwook Park

Younghoon Lee

Hyunjung Park

Jinhyung Lee

Seung-jun Lee

Young Bo Shim

Gyeayoung Kwag

Kyungryun Kim

Junghoon Choi

Byung-Kwon Choi

Youngsung Yang

Kyoungsoo Lee

Yus Ko

ChangHyun Roh

Dongjin Keum

Hyongryol Hwang

Hwa Yeal Yu

Hohyun Shin

Sanghoon Jung

Wonil Bae

Jaeseong Lim

Mikyung Park

Yeiji Bae

Youngho Choe

Young Min Jhon

Juhwa Cheong

Yong Kim

Young-Hwan Kim

Gwang Hwan Lee

Kwangsun Ji

Seungyoon Lee

Chang Hyun Roh

Seungki Hong

Taeyoung Kwon

Jong-Young Kwak

Chun Keun Kim

Younggu Do

Mann Yi

Hongcheol Lee

Sehyun Kwon

Yeji Bae

A memory device includes plural banks that perform a per-bank refresh (PBR) operation, and an address register that provides a single row address signal to two banks of the plural banks, the two banks simultaneously performing the PBR operation and the single row address signal being shared by the two banks. The two banks activate a word line of each memory cell array based on a single decoded row address signal that is generated based on the single row address signal.

Memory device and operation method thereof

A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

Voltage trimming circuit

A method of preparing a polyvinyl alcohol nanofiber membrane includes a material for controlling cell specific adhesion, and a nanofiber membrane that can maintain cellular functions such as cell activity and growth is prepared by adding aqueous solutions containing a polyacrylic acid and a glutaraldehyde crosslinking agent in a polyvinyl alcohol and materials capable of enhancing or regulating cell adhesion, electrospinning, treating with hydrochloric acid vapor and dimethylformaldehyde solvent and treating with sodium hydroxide to control the cell adhesion.

Method of preparing polyvinyl alcohol nanofiber membrane enhancing cell specific adhesion

A method of manufacturing an insole may include providing an electronic element on a support layer; connecting a connector to the support layer; providing the support layer to a lower mold frame; covering the lower mold frame with an upper mold frame; and applying a foam material between the lower mold frame and the upper mold frame.

Method of manufacturing insole

An insole including a base; an electronic element provided to the base; a connection line configured to extend from the electronic element and to pass through the base; and a cover provided on a top surface of the base to cover the electronic element and configured to be separable from the base.

Insole and shoes comprising the same

An insole may include an insole body in a shape receivable in a shoe; an electronic element provided in the insole body; a connection line configured to electrically connect to the electronic element and including a contact terminal exposed to the outside of the insole body; and a connector including a detachable member configured to at least partially protrude outward from the insole body and configured to support the contact terminal.

An electronic device includes a power management integrated circuit (PMIC) including a plurality of regulators. Each of the plurality of regulators has a current meter configured to measure a respective load current. A load device is configured to receive real-time load current information from the PMIC and to perform a performance improvement operation based on the real-time load current information.

Power management integrated circuit for supplying load current information and electronic device having the same

A solar cell includes a semiconductor substrate, a tunneling layer on one surface of the semiconductor substrate, a first conductive type area on the tunneling layer, a second conductive type area on the tunneling layer such that the second conductive type area is separated from the first conductive type area, and a barrier area interposed between the first conductive type area and the second conductive type area such that the barrier area separates the first conductive type area from the second conductive type area.

Solar cell and method for manufacturing the same

The present invention provides a chalcogenide phase-change material represented by the following Chemical Formula 1, and a memory device including the same.M(ASbTe)&#x2003;&#x2003;[Chemical Formula 1] In Chemical Formula 1, M denotes an element having a doping formation energy &#x394;Ein a range of &#x2212;3 eV/atom to 0.5 eV/atom, A denotes indium (In) or germanium (Ge), a and b are each positive numbers and selected to satisfy a+b=1, x ranges from 0.15 to 0.3, and y ranges from 0.05 to 0.25.

Four-or-more-component-based chalcogenide phase-change material and memory device comprising the same

Discussed is a solar cell including a semiconductor substrate including a base area and a doping area, a doping layer formed on the semiconductor substrate, the doping layer having a conductive type different from the doping area, a tunneling layer interposed between the doping layer and the semiconductor substrate, a first electrode connected to the doping area, and a second electrode connected to the doping layer.

A post-processing apparatus of a solar cell carries out a post-processing operation including a main period for heat-treating a solar cell including a semiconductor substrate while providing light to the solar cell. The post-processing apparatus includes a main section to carry out the main period. The main section includes a first heat source unit to provide heat to the semiconductor substrate and a light source unit to provide light to the semiconductor substrate. The first heat source unit and the light source unit are positioned in the main section. The light source unit includes a light source constituted by a plasma lighting system (PLS).

Post-processing apparatus of solar cell

A solar cell module includes a plurality of solar cells comprising a first solar cell and a second solar cell adjacent to each other; a conductive ribbon, wherein each of the plurality of solar cells comprises: a substrate; an emitter layer of positioned on the substrate; a plurality of finger electrodes formed in a first direction, each finger electrode being electrically connected to the emitter layer; and at least one first collector formed in a second direction crossing the first direction, the at least one first collector being electrically connected to the plurality of finger electrodes, wherein the conductive ribbon is attached to the at least one first collector in the second direction by a conductive adhesive, and wherein the conductive ribbon is attached on a collector region where the at least one first collector is formed and a deletion where the at least one first collector is not formed.

Solar cell and method for manufacturing the same, and solar cell module

A method of manufacturing a solar cell is discussed. The method of manufacturing the solar cell includes: forming a conductive region on a semiconductor substrate; forming an electrode connected to the conductive region; and post-processing the semiconductor substrate to passivate the semiconductor substrate. The post-processing of the semiconductor substrate comprises a main processing process for heat-treating the semiconductor substrate while providing light to the semiconductor substrate. A temperature of the main processing process is about 100&#xb0; C. to about 800&#xb0; C., and the temperature and light intensity of the main processing process satisfy Equation of 1750&#x2212;31.8&#xb7;T+(0.16)&#xb7;T&#x2266;I. Here, T is the temperate (&#xb0; C.) of the main processing process, and I is the light intensity (mW/cm) of the main processing process.

Method for manufacturing solar cell

Growing community of inventors

Seoul, South Korea

Minho Choi