Advanced Micro Devices Corporation

Spansion Llc.

Other

Globalfoundries Inc.

Cypress Semiconductor Corporation

Fasl LLC

Infineon Technologies LLC

Vantis Corporation

Advance Micro Devices, Inc.

Advanced Micro Devices, Inc. and Spansion LLC

Adavnced Micro Devices, Inc.

Minh Van Ngo

Paul Raymond Besser

Angela Tai Hui

Christy Mei-Chu Woo

Dawn M Hopper

Robert A Huertas

Arvind Halliyal

Suzette Keefe Pangrle

Lu You

Mark T Ramsbey

Sergey D Lopatin

Steven C Avanzino

William George En

Ning Cheng

Jean Y Yang

Christopher F Lyons

David Keating Foote

Fei Wang

Eric N Paton

Tazrien Kamal

Wenmei Li

Hirokazu Tokuno

Ramkumar Subramanian

Takeshi Nogami

George Jonathan Kluth

Darin A Chan

Hieu T Pham

Qi Xiang

Matthew S Buynoski

Jeffrey Allan Shields

Minh Quoc Tran

Hartmut Ruelke

Jacques J Bertrand

Kuo-Tung Chang

Hidehiko Shiraiwa

Mark S Chang

Pin-Chin Connie Wang

Rinji Sugino

Haihong Wang

Cyrus E Tabery

Richard J Huang

James N Pan

Olov B Karlsson

Chih-Yuh Yang

Kashmir S Sahota

Simon S Chan

Shekhar Pramanick

Nicholas H Tripsas

Joong Jeon

Scott Allan Bell

Ming-Ren Lin

Amit P Marathe

Alexander H Nickel

Paul L King

Kouros Ghandehari

Amol Ramesh Joshi

Jaeyong Park

Zoran Krivokapic

Hiroyuki Kinoshita

Khanh Q Tran

Wenge Yang

John Espinoza Sanchez, Jr

Guarionex Morales

Robin W Cheung

Sunil D Mehta

Errol Todd Ryan

Joerg Hohage

Krishnashree Achuthan

Simon Siu-Sing Chan

Sey-Ping Sun

Connie Pin-Chin Wang

Bhanwar Singh

Hiroyuki Ogawa

Yu Nan Sun

Chi K Chang

Effiong Etukudo Ibok

Yider Wu

Robert B Ogle

Khanh B Nguyen

Jung-Suk Goo

Tim Z Hossain

Hamid Partovi

YongZhong Hu

Chun Jiang

Jayendra D Bhakta

Mark I Gardner

Thorsten E Kammler

William S Brennan

Yi He

Ankur Agarwal

Uzodinma Okoroanyanwu

Richard Paul Kingsborough

Shankar Sinha

Kuo Tung Chang

Jean Yee-Mei Yang

Mehrdad Mahanpour

Susan H Chen

Raymond T Lee

Diana M Schonauer

Atul Gupta

In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

Contacts for semiconductor devices

A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.

A semiconductor component and a method for manufacturing the semiconductor component that are suitable for use with low temperature processing. A semiconductor substrate is provided and an optional layer of silicon nitride is formed on the semiconductor substrate using Atomic Layer Deposition (ALD). A layer of dielectric material is formed on the silicon nitride layer using Sub-Atmospheric Chemical Vapor Deposition (SACVD) at a temperature below about 450&#xb0; C. When the optional layer of silicon nitride is not present, the SACVD dielectric material is formed on the semiconductor substrate. A contact hole having sidewalls is formed through the SACVD dielectric layer, through the silicon nitride layer, and exposes a portion of the semiconductor substrate. A layer of tungsten nitride is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact hole. Tungsten is formed on the layer of tungsten nitride.

Method for manufacturing a contact for a semiconductor component and related structure

A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

Etch stop layer for memory cell reliability improvement

A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

Method for forming a semiconductor layer with improved gap filling properties

A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.

Void free interlayer dielectric

During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 &#x212b; to about 500 &#x212b;, curing after deposition, as by UV radiation or by heating at a temperature of about 400&#xb0; C. to about 1000&#xb0; C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

Gap-filling with uniform properties

A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Buried silicide local interconnect with sidewall spacers and method for making the same

A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% Nwith less than 10% H, performing planarization, performing in-situ low-H NHplasma treatment and low Si&#x2014;H SiN etch stop layer deposition, and performing remaining back end processing.

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Method for forming a semiconducting layer with improved gap filling properties

Growing community of inventors

Fremont, CA, United States of America

Minh Van Ngo