Ati International Srl

Toshiba America Electronic Components, Inc.

Centillium Communications, Inc.

Minh V Watson

Crist Y Lu

Hessam Mohajeri

Tung Tran

The invention relates to an apparatus comprising a pipelined converter, such as a pipelined ADC. The pipelined converter has a first set of stages and a second set of stages. A clocking circuit is configured to generate a plurality of clocking signals for the pipelined converter. The plurality of clocking signals comprise a first clocking signal at a first voltage level that is provided to the first set of stages and a second clocking signal at a second voltage level that is provided to the second set of stages.

Pipelined converter

In an example embodiment, an apparatus, such as a two stage operational amplifier, comprising a first stage amplifier having an input and an output, and a second stage amplifier having an input and an output, the input of the second stage amplifier is coupled to the output of the first stage amplifier. A first bias circuit is operable to set a common mode voltage of the first amplifier. A second bias circuit is operable to set a common mode voltage of the second amplifier. A first feedback circuit is coupled to the first bias circuit and the output of the first stage. The first feedback circuit is operable to control the common mode voltage of the first stage amplifier based on the common mode voltage set by the first bias circuit and the output of the first stage amplifier.

Threshold voltage compensation for a two stage amplifier

A digital-to-analog converter includes a number of current steering cells. In each current steering cell, a current source is biased by a differential amplifier to provide a high output impedance. The high output impedance in the current steering cell allows the digital-to-analog converter to operate under low supply voltage conditions.

Digital-to-analog converter with improved output impedance switch

An Analog-to-Digital Converter (ADC) contains two pipeline stages that operate in parallel on two different analog samples. Each pipeline stage includes two sub-stages. Each sub-stage has a low-resolution ADC element and a low-resolution DAC element. The ADC element converts the analog voltage input to the sub-stage into B digital bits, where B is a low number such as 1, 1.5, or 2. These digital bits are re-converted back to an analog DAC voltage by the DAC element. A subtractor then subtracts the analog DAC voltage from the sub-stage's analog input voltage to produce a difference voltage that represents the quantization error of the ADC/DAC elements. A multiplying amplifier multiplies the difference voltage by 2,to generate an output voltage to the next sub-stage. Each high-level pipeline stage acts as a recycling ADC, having a feedback switch that connects the output of the last sub-stage to the analog input of the first sub-stage. During successive clock periods, the first sub-stage converts B digital bits during a PH,phase while the last sub-stage converts another B digital bits of less significance during the PH,phase. The analog output from the last sub-stage is recycled back to the first sub-stage for the next clock and another 2B bits are converted in the next clock period. Once all of the MSB's have been converted, the last sub-stage outputs an analog residue voltage to the first sub-stage of the second pipeline stage, which then converts the LSB bits over several clock cycles using the same recycling method.

Two-stage pipelined recycling analog-to-digital converter (ADC)

A time-multiplexed common mode feedback circuit provides a common mode feedback signal during active phases of a clock signal. The common mode feed back circuit includes capacitors which are charged during the inactive phases of the clock signals. In one embodiment, the common mode feedback signal is provided by two generator circuits each driven by a respective one of two non-overlapping clock signals. In that embodiment, the generator circuits provide the common mode feedback signal during the active phases of their respective clock signals.

Time interleaved common mode feedback circuit with process compensated bias

A digital-to-analog converter (DAC) uses switched capacitors summed, to an op amp to generate the analog output voltage. Least-significant-bits (LSBs) of the digital input switch a reference voltage to binary-weighted capacitors. The most-significant-bits (MSBs) are thermometer-coded and switch the reference voltage to capacitors that have a same size, double the size of the maximum LSB's capacitor. The thermometer-coded MSB's are scrambled before switching the same-size capacitors so that the assignment of a digital input bit to a capacitor varies from sample to sample. Any variation in capacitances for the same-size capacitors is thus spread to different digital values so that errors do not occur consistently for the same digital values. The scrambler uses radix-2 butterflies to swap bit assignments and thus outputs an even number of signals to the capacitors. Since the thermometer code is an odd number of signals, an extra signal is present that is always driven high or low. Scrambling makes the location of the extra signal unknown. A dummy same-size capacitor is driven to an opposite voltage to compensate for the extra signal. The DAC is further divided into two stages, with the lower stage scaled down to the minimum capacitor size by a linking capacitor to the upper stage.

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Fremont, CA, United States of America

Minh V Watson