Intel Corporation

Minh T Le

Rahul Khanna

Eugene Gorbatov

Ulf Hanebutte

Howard S David

Thanunathan Rangarajan

Kshitij Arun Doshi

Naoki Matsumura

Rafael De La Guardia Gonzalez

Thomas A Boyd

Bijoyraj Sahu

Craig J Jahne

Christopher Wade Ackerman

Edgar J Unrein

Evan A Chenelly

Carlos Alvizo Flores

Ron D Egger

Chris H Hanes

Charles Rego

Richard Marian Thomaiyar

Ulf R Hanebutte

A battery that periodically checks an actual battery capacity or energy with charge to a preset voltage (e.g., 4.1 V). The battery then decides the battery capacity or energy. If the capacity or energy is insufficient, then an apparatus in or associated with the battery slightly increases charging voltage to a point where the capacity is sufficient (e.g. from 4.1 V to 4.11 V). The process of periodically checking and slightly increasing charging voltage is performed until charging voltage reaches specification limit (e.g., 4.2 V). The scheme described herein has benefits such as battery longevity can be extended, risk of insufficient energy reserve can be reduced, burst power can be used as long as possible, and/or even higher burst power can be used.

Apparatus and method to provide dynamic battery charging voltage

Systems, apparatuses, methods, and computer-readable media are presented for managing an apparatus for thermal energy management including a first container. The first container includes a first cavity, and is configured to hold a first liquid coolant within the first cavity to at least partially surround a second container. The second container includes a second cavity configured to hold one or more heat sources, and a second liquid coolant to at least partially surround the one or more heat sources. The second container is sealed to separate the first liquid coolant from the second liquid coolant. Other embodiments may be described and/or claimed.

Modular thermal energy management designs for data center computing

In an embodiment, a processor includes a fuzzy thermoelectric cooling (TEC) controller to: obtain a current TEC level associated with the processor; obtain a current fan power level associated with the processor; fuzzify the current TEC level to obtain a first fuzzy fan level; fuzzify the current fan power level to obtain a second fuzzy fan level; determine a new TEC power level based at least in part on the first fuzzy fan level, the second fuzzy fan level, and a plurality of fuzzy rules; and provide the new TEC power level to a TEC device associated with the processor, where the TEC device is to transfer heat from the processor to a heat sink. Other embodiments are described and claimed.

Fuzzy logic control of thermoelectric cooling in a processor

Technologies for distributed durable data replication include a computing device having persistent memory that stores a memory state and an update log. The computing device isolates a host partition from a closure partition. The computing device may sequester one or more processor cores for use by the closure partition. The host partition writes transaction records to the update log prior to writing state changes to persistent memory. A replication service asynchronously transmits log records to a remote computing device, which establishes a replica update log in persistent memory. If the host partition fails, the closure partition transmits remaining log records from the update log to the remote computing device. The update log may be quickly replayed when recovering the computing device from failure. The remote computing device may also replay the replica update log to update a remote copy of the state data. Other embodiments are described and claimed.

Distributed persistent memory using asynchronous streaming of log records

In an embodiment, a processor includes a thermoelectric cooling (TEC) controller to obtain a platform cooling level associated with the processor; obtain a temperature associated with the processor; calculate a TEC power level based at least in part on the platform cooling level and the temperature; and provide the TEC power level to a TEC device associated with the processor, wherein the TEC device is to transfer heat from the processor to a heat sink. Other embodiments are described and claimed.

Adaptive thermoelectric cooling in a processor

In one embodiment, the present invention includes a power manager to receive a memory power usage value, to determine an available power based at least in part on a power budget and the memory power usage value, and to change a memory power state based at least in part on the available power, wherein the memory power state comprises a memory frequency and a memory voltage. Other embodiments are described and claimed.

Method and apparatus to limit memory power

Memory power estimation by means of calibrated weights and activity counters are generally presented. In this regard, in one embodiment, a memory power is introduced to read a value from a memory activity counter, to determine a memory power estimation based at least in part on the value and a calibration, and to store the memory power estimation to a register. Other embodiments are also described and claimed.

Memory power estimation by means of calibrated weights and activity counters

An improved assembly for a computer that includes a motherboard having a first side and a second side. The first side has a first portion and a second portion. The first portion contains components capable of generating substantial heat and a strong electric field. The assembly further includes an EMI attenuating cover that encloses the first portion of the first side of the motherboard, but does not enclose the second portion of the first side of the motherboard.

Growing community of inventors

Olympia, WA, United States of America

Minh T Le