Advanced Micro Devices Corporation

Spansion Llc.

Other

Globalfoundries Inc.

Cypress Semiconductor Corporation

Western Digital (fremont), Inc.

Advanced Micro Devices, Inc. and Spansion LLC

Minh Quoc Tran

Lu You

Minh Van Ngo

Alexander H Nickel

Sergey D Lopatin

Pin-Chin Connie Wang

Fei Wang

Paul Raymond Besser

Hieu T Pham

Erik Wilson

Lynne A Okada

Robert A Huertas

Minh-Van Ngo

Hirokazu Tokuno

Matthew S Buynoski

Christy Mei-Chu Woo

Jeremias D Romero

Steven C Avanzino

Jeffrey Allan Shields

Sung Jin Kim

Jeong-Uk Huh

Suzette Keefe Pangrle

Simon S Chan

William S Brennan

Nicholas H Tripsas

Amit P Marathe

Ning Cheng

Juri Krieger

Inkuk Kang

Connie Pin-Chin Wang

Joffre F Bernard

Pei-Yuan Gao

Igor Sokolik

Allen Lewis Evans

Jerry Cheng

Amir Hossein Jafarpour

Alline F Myers

Sateeshchandra S Bajikar

The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.

Electrically programmable and eraseable memory device

An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.

High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance

The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.

Electrically programmable and erasable memory device and method of fabrication thereof

A proximity sensor is described including a capacitor formed by a first conductive element and a second conductive element. The first conductive element and the second conductive element are situated at a magnetic head, a slider that connects to the magnetic head, a reader of the magnetic head, a writer of the magnetic head, a reader shield of the magnetic head, or a writer shield of the magnetic head. A capacitance and a fringing electric field are formed by the capacitor when there is a voltage difference between the first conductive element and the second conductive element. The capacitor is situated such that the fringing electric field changes with a positioning change of a magnetic storage medium with respect to at least one of the first conductive element and the second conductive element. The capacitor is also situated such that the capacitance changes with the fringing electric field change.

Capacitance sensor for determining a distance between a head and a magnetic storage medium

During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 &#x212b; to about 500 &#x212b;, curing after deposition, as by UV radiation or by heating at a temperature of about 400&#xb0; C. to about 1000&#xb0; C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

Gap-filling with uniform properties

A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% Nwith less than 10% H, performing planarization, performing in-situ low-H NHplasma treatment and low Si&#x2014;H SiN etch stop layer deposition, and performing remaining back end processing.

[object Object]

Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an Natmosphere containing low Hor no H, and at temperatures less than 200&#xb0; C., e.g., 100&#xb0; C. to 150&#xb0; C.

Cu annealing for improved data retention in flash memory devices

Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.

Ordered porosity to direct memory element formation

Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si&#x2014;H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si&#x2014;H bonds on the first silicon nitride layer for reduced charge loss.

Semiconductor devices with copper interconnects and composite silicon nitride capping layers

An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.

Ultra low dielectric constant integrated circuit system

Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.

Sealing sidewall pores in low-k dielectrics

The subject invention provides systems and methodologies for fabrication of memory and/or selection (e.g., diodes) elements in a recession in a semiconductor layer. In particular, a trench of varying width is created in the semiconductor layer by employing various etching techniques. A metal film can be deposited in the trench according to a desired deposition thickness in order to seam close a narrow portion of the trench while form a dimple in a wide portion of the trench. The trench, after metal film deposition, exhibits a depression in wider trench portions relative to narrow trench portions. The depression can be utilized by placing one or more memory or selection layers in the depression, and a via can be formed over a portion of the trench to form an interconnect.

Systems and methods for a memory and/or selection element formed within a recess in a metal line

An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition

Disclosed are methods and structures for fabrication of reliable and efficient memory cells. The methods involve formation of a conformal diffusion barrier layer in a via, deposition of an electrode material in the via, removal of a certain portion of the electrode material from the via to expose a the portion of the diffusion barrier layer, converting the exposed portion of the diffusion barrier layer into an oxide, forming a memory element film, and forming and patterning a top electrode. Improved electrical conduction and data retention from the memory element of a memory cell by preventing short circuits and leakage of current through the conductive diffusion barrier layer, and thereby enhanced reliability and performance of a memory cell are obtained.

Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film

Growing community of inventors

Milpitas, CA, United States of America

Minh Quoc Tran