International Business Machines Corporation

Minh H Tong

Edward J Nowak

Andres Bryant

William F Clark, Jr

Xiaowei Tian

Robert J Gauthier, Jr

Steven H Voldman

John J Ellis-Monaghan

Jed Hickory Rankin

Wilbur David Pricer

Jeffrey Scott Brown

Wai-Ming William Au

William R Tonti

Edward P Maciejewski

Dale E Pontius

Stephen Scott Furkay

Michael A Roberge

Donald J Cook

Jack Allan Mandelman

Claude Louis Bertin

Terence B Hook

Kirk David Peterson

Kerry Bernstein

Clark Debs Jeffries

Randy William Mann

Howard L Kalter

Erik L Hedberg

Jerome Brett Lasky

Lawrence G Heller

Ronald Jay Bolam

Francis H Chan

Endre P Thoma

Stephen Frank Geissler

Klaus Helwig

William D Clark

John E Bertsch

Wolfdieter Lohlein

Jeffery S Hines

The amount of chip power that is consumed for cache storage size maintenance is optimized by the close monitoring and control of frequency of missed requests, and the proportion of frequently recurring items to all traffic items. The total number of hit slots is measured per interval of time and is compared to the theoretical value based on random distribution. If the missed rate is high, then the observed effect and value of increasing cache size are deduced by observing how this increase affects the distribution of hits on all cache slots. As the number of frequently hit items in proportion to the total traffic items increases, the benefits of increasing the cache size decreases.

Automatic cache activation and deactivation for power reduction

A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.

Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure

A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor comprising at least body region and diffusion regions buried interconnect plane optionally self-aligned to diffusion regions and in contact with body region isolation oxide region between diffusion regions and buried interconnect plane and buried oxide layer present beneath buried interconnect plane

Active well schemes for SOI technology

An SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region has a width and extends from a surface of the substrate layer downward into contact with the insulator layer along a portion of the width and extends only partially into the substrate layer along another portion of the width. The SOI multiple FET structure also includes a pair of gates on the surface of the substrate layer each overlapping one of the distal diffusion regions and the central diffusion region; and a pair of body regions in the substrate layer each under one of the gates for forming a channel between the one of the distal diffusion regions and the central diffusion region. The body regions are in electrical communication under the another portion of the width of the central diffusion region. Methods for forming the SOI multiple FET structure are also provided.

Matched transistors and methods for forming the same

A silicon on insulation device having halo extensions of source and drain regions and an additional implant for inducing silicon lattice damage is able to withstand high operating voltages. A field lowering Lightly Doped Drain implant and removal of standard damaging source implants decreases avalanche currents and significantly increases drain-to-source breakdown voltage.

Asymmetric high voltage silicon on insulator device design for input output circuits

A semiconductor device including an SOI substrate; a plurality of diffusion regions in substrate, separated by, and abutting a plurality of body regions in said substrate, a first one of the body regions and its abutting diffusion regions having a first width and successive ones of the body regions and their abutting diffusion regions having successively smaller widths; and a plurality of gates each over one of the plurality of body regions and separated from the body regions by a dielectric material, said plurality of gates connected to a common voltage terminal.

High-voltage high-speed SOI MOSFET

An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10 Ohms&minus;um divided by the width of the pass-gate.

SOI pass-gate disturb solution

A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings. During this step the first type dopant is disposed into the gate. The substrate having the first type dopant comprises one terminal of the capacitor and the gate comprises another terminal of the capacitor.

Methods for forming decoupling capacitors

A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor comprising at least body region and diffusion regions ; buried interconnect plane optionally self-aligned to diffusion regions and in contact with body region ; isolation oxide region 118 between diffusion regions and buried interconnect plane ; and buried oxide layer present beneath buried interconnect plane

Described is a dynamic threshold field effect transistor (DTFET) that includes a gate-to-body contact structure within the gate. By forming the gate-to-body contact structure that can reduce the gate-to-body contact resistance and increase the device packing density, the DTFET can be used in silicon on insulator (SOI) technologies and take full advantages of the DT-CMOS performance benefit.

Dynamic threshold voltage devices with low gate to substrate resistance

A device, having circuits formed thereon, comprises a circuit including a frequency generator for generating a detectable radio frequency energy when powered and a power generator, coupled to the frequency generator, for generating power when exposed to light.

Contact-less probe of semiconductor wafers

A semiconductor device having an SOI FET comprising a silicon body on an insulating layer on a conductive substrate. A gate dielectric and a gate are provided on a surface of the silicon body, and a source and a drain are provided on two sides of the gate. A buried body contact to the substrate conductor is provided below a third side of the gate. The buried body contact does not extend to the top surface of the silicon body. The body contact is separated from the gate by a second dielectric having a thickness typically greater than that of the gate dielectric. The body contact is a plug of conductive material, and the second dielectric coats the body contact under the gate. The FET can be used in an SRAM circuit or other type of circuit having a silicon-on-insulator (SOI) construction.

Method and structure for creating high density buried contact for use with SOI processes for high performance logic

A monitor for detecting pass gate leakage in a silicon on insulator device and a method for using the same is described herein. A pulse generator supplies a signal to a set of buffers connected in parallel, which pass on a signal to the source side of a series of NFETs. The plurality of NFETs are ordered by increasing channel widths. The NFETs have grounded gates, and therefore will not pass current due to field effects. Each NFET is connected to a latch, and the latches are originally set to the same state. When the signal supplied to the NFET drops from high to low, pass gate leakage will occur through the channel of each NFET. If pass gate leakage through any given NFET is sufficient, the latch will change states. The latch output signal is sent to a shift register, which can be made to output information. By incorporating the monitor on the chip, pass gate leakage tolerances and specifications can be established in-line during manufacture.

SOI pass gate leakage monitor

Disclosed is a static CMOS circuit having an input and an output, comprising: a pass gate switch fabricated from thick oxide devices coupled between the input and a fast CMOS circuit fabricated from thin oxide devices, the fast CMOS circuit coupled to the output; and a slow CMOS circuit fabricated from thick oxide devices coupled between the input and the output.

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Essex Junction, VT, United States of America

Minh H Tong