Texas Instruments Corporation

Minh Chau

Hugh Thomas Mair

Uming U Ko

Alice Wang

Bixia Li

James Sangwon Song

Achuta Reddy Thippana

An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a 'glitch-free' control for a power switch.

Apparatus, system and method of power state control

In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal and the received non-divided input clock signal, the first output signal being associated with a first delay. The method further includes, at a delay line, receiving the non-divided input signal, delaying the non-divided input signal for a time substantially equivalent to the first delay, and generating a second output clock signal associated with a second delay substantially equal to the first delay. The method further includes: (1) receiving at a multiplexer the first output signal, the second output signal, and a select control signal indicating which of the first output signal or the second output signal to select; (2) selecting at the multiplexer either the received first output signal or the second output signal based on the select control signal; and (3) generating the selected first output signal or second output signal as a substantially balanced third output signal.

System and method for reducing clock skew

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Carrollton, TX, United States of America

Minh Chau