Intermolecular, Inc.

Novellus Systems Incorporated

Guardian Industries Corporation

Guardian Glass, LLC

Minh Anh Nguyen

Zhi-Wen Sun

Guowen Ding

Guizhen Zhang

Nitin Kumar

Minh Le

Nikhil D Kalyankar

Mohd Fadzli Anwar Hassan

Chi-I Lang

Richard Blacker

Yiwei Lu

Judy H Huang

Jingyu Lao

Hien Minh Huu Le

Yu Wang

Thai Cheng Chua

Sunil Shanker

Wenxian Zhu

Dipankar Pramanik

Jian Li

Milind Ganesh Weling

Vidyut Gopal

Sandeep Nijhawan

Jeroen Van Duren

David Chi

Craig Hunter

Sagar Vijay

Sean Cox

Ken Vo

Mohd Fadzil Anwar Hassan

A substrate having a plurality of site-isolated regions defined thereon is provided. A first electrochromic material, or a first electrochromic device stack, is formed above a first of the plurality of site-isolated regions using a first set of processing conditions. A second electrochromic material, or a second electrochromic device stack, is formed above a second of the plurality of site-isolated regions using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.

Combinatorial methods for developing electrochromic materials and devices

Coated articles are disclosed. The coated articles include a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1. 5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack can have improved ductility property.

Silver based conductive layer for flexible electronics

Embodiments provided herein describe a low-e panel and a method for forming a low-e panel. A transparent substrate is provided. A metal oxide layer is formed over the transparent substrate. The metal oxide layer includes a first element, a second element, and a third element. A reflective layer is formed over the transparent substrate. The first element may include tin or zinc. The second element and the third element may each include tin, zinc, antimony, silicon, strontium, titanium, niobium, zirconium, magnesium, aluminum, yttrium, lanthanum, hafnium, or bismuth. The metal oxide layer may also include nitrogen.

Low-e panels with ternary metal oxide dielectric layer and method for forming the same

The present disclosure includes a texture formulation that includes an aliphatic diol, an alkaline compound and water which provides a consistent textured region across a silicon surface suitable for solar cell applications. The current invention describes silicon texturing formulations that include at least one high boiling point additive. The high boiling point additive may be a derivative compound of propylene glycol or a derivative compound of ethylene glycol. Processes for texturing a crystalline silicon substrate using these formulations are also described. Additionally, a combinatorial method of optimizing the textured surface of a crystalline silicon substrate is described.

Silicon texturing formulations

Embodiments provided herein describe electrochromic devices and methods for forming electrochromic devices. The electrochromic devices include a transparent substrate, a transparent conducting oxide layer coupled to the transparent substrate, and a layer of electrochromic material coupled to the transparent conducting oxide layer. The transparent conducting oxide layer includes indium and zinc.

Electrochromic device with improved transparent conductor and method for forming the same

Low-E panels with ternary metal oxide dielectric layer and method for forming the same

Embodiments provided herein describe a low-e panel and a method for forming a low-e panel. A transparent substrate is provided. A metal oxynitride layer is formed over the transparent substrate. The metal oxynitride layer includes a first metal and a second metal. A reflective layer is formed over the transparent substrate.

Low-E panel with improved dielectric layer and method for forming the same

Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.

Resistive random access memory cells having doped current limiting layers

Embodiments of the current invention describe methods of forming different types of crystalline silicon based solar cells that can be combinatorially varied and evaluated. Examples of these different types of solar cells include front and back contact silicon based solar cells, all-back contact solar cells and selective emitter solar cells. These methodologies all incorporate the formation of site-isolated regions using a combinatorial processing tool and the use of these site-isolated regions to form the solar cell area. Therefore, multiple solar cells may be rapidly formed on a single crystalline silicon substrate for use in combinatorial methodologies. Any of the individual processes of the methods described may be varied combinatorially to test varied process conditions or materials.

Methods of building crystalline silicon solar cells for use in combinatorial screening

Embodiments of the current invention include methods of improving a process of forming a textured TCO film by combinatorial methods. The combinatorial method may include depositing a TCO by physical vapor deposition or sputtering, annealing the TCO, and etching the TCO where at least one of the depositing, the annealing, or the etching is performed combinatorially. Embodiments of the current invention also include improved methods of forming the TCO based on the results of combinatorial testing.

Combinatorial screening of transparent conductive oxide materials for solar applications

Surface texturing of the transparent conductive oxide (TCO) front contact of a thin film photovoltaic (TFPV) solar cell is needed to enhance the light-trapping capability of the TFPV solar cells and thus improving the solar cell efficiency. Embodiments of the current invention describe chemical formulations and methods for the wet etching of the TCO. The formulations and methods may be optimized to tune the surface texturing of the TCO as desired.

Acid chemistries and methodologies for texturing transparent conductive oxide materials

This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness variations by employing the method using a passivation treatment and precoating of the chamber before substrates are processed. In a preferred process, after each wafer of a batch is finished, the passivation steps are repeated. In a further preferred process, after all the wafers of a batch are finished, the passivation and precoat procedure is repeated. A preferred passivation gas is a mixture of hydrogen and oxygen.

H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift

Plasma etch processes incorporating H/Noble gas etch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen and one or more Noble gases as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Growing community of inventors

San Jose, CA, United States of America

Minh Anh Nguyen