National Semiconductor Corporation

Mingwei Xu

Jamal Ramdani

Steven J Adler

A system and method are disclosed for providing a self aligned bipolar transistor using a silicon nitride ring. An active region of the transistor is formed and a sacrificial emitter is formed above the active region of the transistor. A silicon nitride ring is formed around the sacrificial emitter. The sacrificial emitter and the silicon nitride ring are formed by depositing a layer of silicon nitride material over the active area of the transistor and performing an etch process to simultaneously create both the sacrificial emitter and the silicon nitride ring. The silicon nitride ring provides support for forming a raised external base for the transistor.

System and method for providing a self aligned bipolar transistor using a silicon nitride ring

A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.

System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter

A system and method are disclosed for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture. The transistor of the present invention comprises a non-selective epitaxial growth (NSEG) collector, an NSEG base, an NSEG emitter and a raised external base that is formed by the selective epitaxial growth (SEG) of a doped polysilicon layer.

System and method for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture

A system and method are disclosed for providing an improved polyemit module for a self aligned heterojunction bipolar transistor architecture. The polyemit module of the transistor of the present invention is formed using a double layer deposition process. In the double layer deposition process, the first layer is a layer of emitter polysilicon and the second layer is a sacrificial layer of silicon germanium (SiGe). The shape and thickness of the emitter polysilicon layer of the polyemit module provides (1) a reduction in the overall resistance of the emitter and (2) an increase in the contact area between the emitter polysilicon layer and a contact structure that is more than three times the contact area that is provided in prior art polyemit modules.

System and method for providing a polyemit module for a self aligned heterojunction bipolar transistor architecture

A system and method are disclosed for providing a self aligned bipolar transistor using a sacrificial polysilicon external base. An active region of a transistor is formed and a sacrificial polysilicon external base is formed above the active region of the transistor and covered with a silicon oxide layer. Then an emitter window is etched and filled with silicon nitride. An etch procedure is subsequently performed to remove the sacrificial polysilicon external base. A layer of doped polysilicon material is then deposited to fill a cavity within the transistor formed by the removal of the sacrificial polysilicon external base. A polysilicon emitter structure is subsequently formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.

System and method for providing a self aligned bipolar transistor using a sacrificial polysilicon external base

A system and method are disclosed for providing a fully self aligned bipolar transistor using modified cavity formation to optimize selective epitaxial growth. A collector of a transistor is formed and at least two layers of silicon oxide are formed above the collector and covered with a polysilicon external raised base. Then an emitter window is etched through the polysilicon external raised base down to the top layer of silicon oxide. A wet etch process is performed to form a cavity in the at least two layers of silicon oxide. Different wet etch rates of the silicon layers with respect to the wet etch process cause the cavity to be formed with a shape that optimizes selective epitaxial growth in the cavity. Polysilicon rich corners and a monocrystalline silicon base are then formed within the cavity.

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South Portland, ME, United States of America

Mingwei Xu