Maxlinear, Inc.

Mingrui Zhu

Timothy Leo Gallagher

Anand Anandakumar

Sheng Ye

Xuefeng Chen

Pawandeep Taluja

Curtis Ling

Arun Kedambadi

Seung Chul Hong

Anand Anandakumer

Methods and systems are provided for adaptive guard interval (GI) combining. A signal carrying a symbol that is preceded by a guard interval (GI) that includes a portion of the symbol may be received, and a portion of the GI that is free from inter-symbol interference (ISI) may be determined. Only a part of the ISI-free portion of the GI may be selected. The selected part of the ISI-free portion of the GI may be less than a whole of the ISI-free portion. The selection may be configured based on a parameter that is applied to a function used in extracting the symbol. The parameter may be a timing adjustment, relative to a start of the symbol, applied to the function when extracting the symbol. Only the part of the ISI-free portion of the GI may then be extracted and combined with a corresponding portion of the symbol.

Method and system for adaptive guard interval (GI) combining

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation

Methods and systems are provided for low-power decoding. An example system may include one or more storage circuits and a decoder circuit. The decoder circuit may implement a plurality of nodes for use during decoding, including at least one data generating node and at least one data checking node, and the storage circuits may store status information associated with the nodes, the status information indicating when each corresponding node is locked or unlocked. During decoding operations, the decoder circuit may set the status information to lock one or more of the nodes based on one or more locking conditions, and may cease decoding based on one or more ceasing conditions. The decoder circuit may locks a data generating node when a corresponding calculated value meets a particular condition, and may lock a data checking node when all data generating nodes associated with it are locked.

Low-power low density parity check decoding

Methods and systems are provided for adaptive guard interval (GI) combining. When a signal carrying at least one symbol that is preceded by a guard interval that comprises a portion of the symbol is received, a portion of the guard interval that is free from inter-symbol interference (ISI) may be determined, and only a part of the ISI-free portion of the guard interval may be extracted. The part of the ISI-free portion of the guard interval may be selected based on timing adjustment, relative to start of the symbol, that is applied to a function used in extracting the symbol. The extracted part of the ISI-free portion of the guard interval may then be combined with a corresponding portion of the symbol. The extracting and/or combining may be performed after a determination that a delay spread is smaller than a predetermined channel delay.

In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

A method and system for combining a guard interval and a corresponding portion of a received symbol, whereby when receiving a signal that contains the symbol with a guard interval corresponding to the symbol, a portion of the guard interval that is free from inter-symbol interference may be extracted, and the extracted portion of the guard interval may be combined with the corresponding portion of the symbol. The extracting and combining may be done after a determining, based on a delay profile provided by the received signal, that a delay spread is smaller than a predetermined channel delay. The delay spread may be determined by filtering an instantaneous delay spread associated with the received signal. The filtering may be performed using a 1-tap infinite impulse response low-pass filter. The low-pass filter may include a time constant that is the inverse of a maximum Doppler frequency shift.

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may include a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

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Irvine, CA, United States of America

Mingrui Zhu