Columbia University

Arizona State University

Texas Instruments Corporation

Mingoo Seok

Jae-sun Seo

Shihui Yin

Zhewei Jiang

Manish Goel

Peter R Kinget

Jing-Fei Ren

Teng Yang

Jiangyi Li

Bo Zhang

Jonghyun Oh

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS/W) at 40 megahertz (MHz) with a 1 volt (V) supply.

Programmable in-memory computing accelerator for low-precision deep neural network inference

Compute-in-memory (CIM) devices and methods for performing vector-matrix multiplication (VMM) are provided. The disclosed CIM device can include a static random access memory (SRAM) array. The SRAM array can include a plurality of column structures. Each column structure can include eight sub-column structures. Each sub-column structure can include at least one bitcell sharing a pair of a local bitline (LBL) and LBLb that can be connected to a pair of global bitlines (GBL) via switches. Each sub-column comprises at least one NOR gate. An even-numbered bitcell can include a wordline 1 (WL1) for a left access transistors, and an odd-numbered bitcell can include a wordline 2 (WL2) for a right access transistors. Every eight columns (8 columns) can be configured to share a hybrid compressor adder-tree (HCA), followed by a bit-first accumulation (BFA).

6T-SRAM-based digital computing-in-memory circuits supporting flexible input dimension

In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as 'C3SRAM') is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments.

Circuits and methods for in-memory computing

A static random-access memory (SRAM) system includes SRAM cells configured to perform exclusive NOR operations between a stored binary weight value and a provided binary input value. In some embodiments, SRAM cells are configured to perform exclusive NOR operations between a stored binary weight value and a provided ternary input value. The SRAM cells are suitable for the efficient implementation of emerging deep neural network technologies such as binary neural networks and XNOR neural networks.

Static random-access memory for deep neural networks

Systems and methods for providing assistance for performing a physically unclonable function (PUF) are provided. Disclosed systems can include a PUF bitcell including at least two voltage-compensated proportional-to-absolute (PTAT) generators, each of which can be configured to generate a first voltage and a second voltage that is different from the first voltage by a voltage difference. The voltage difference can be resistant to temperature variations and variations, if any, in the supply voltage. The system can further include a comparator, which can be electrically coupled to each of the at least two PTAT generators, and can be configured to receive the first voltage and the second voltage generated therefrom, determine a polarity of each of the voltage differences, and generate a random bit.

Voltage and temperature compensated device for physically unclonable function

Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.

Circuits, methods, and media for detecting and countering aging degradation in memory cells

An embodiment of the invention provides a cryptographic device that draws a substantially constant current from an accessible electrical node that supplies power to the cryptographic device. Keeping the current drawn from the accessible electrical node substantially constant reduces the probability that secure information may be taken by unwanted third parties from the cryptographic device. The cryptographic device includes an active shunt current regulator, a low-pass filter, a linear voltage regulator and an AES (advanced encryption standard) circuit.

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New York, NY, United States of America

Mingoo Seok