Altera Corporation

Didrew Technology (bvi) Limited

Chengdu Eswin Sip Technology Co., Ltd.

Beijing Eswin Technology Co., Ltd.

Minghao Shen

Xiaotian Zhou

Chunbin Zhang

Yijiang Hu

Shaolin Zou

Xiaoming Du

Vincent Hool

Disclosed is a method of manufacturing a semiconductor device that includes securing a lower surface of a wafer to a supporting surface of a carrier substrate formed of copper or other metal having good thermal conductance. Further semiconductor processing for packaging can include forming an RDL on the wafer, etching scribe channels through the wafer, and coating the wafer with encapsulant. After dicing, the metal carrier remains in contact with and supporting the lower surface of the wafer, and the remainder of the wafer remains coated by the encapsulant.

Encapsulated fan-in semiconductor package with heat spreader and method of manufacturing the same

Disclosed is an adhesive composition for temporarily bonding a semiconductor workpiece and support carrier pair with improved adhesive film properties. The adhesive composition may include one or more polymer resins, solvents, and a small but critical quantity of surfactants, among others. In operation, the one or more surfactants may improve film continuity, leveling, and reduce voids and defects. Sample semiconductor workpiece includes a semiconductor silicon wafer and sample support carrier includes rigid semiconductor silicon or glass, sapphire or other rigid materials.

Adhesive composition for temporary bonding of semiconductor workpiece and support carrier pair

Disclosed is a semiconductor device and method of manufacturing a semiconductor device that includes planarizing surfaces of a semiconductor substrate and a carrier substrate and then placing the semiconductor substrate on the carrier substrate such that the planarized surfaces of each are adjoining and allowing the semiconductor substrate to bond to the carrier substrate using a Van der Waals force. The method also includes forming a metal filled trench around the semiconductor substrate and in contact with the carrier substrate, which can also be formed of metal. The metal filled trench and carrier substrate together form a metal cage-like structure around the semiconductor substrate that can serve as a heat sink, integrated heat spreader, and Electro-Magnetic Interference shield for the semiconductor substrate.

Hermetic flat top integrated heat spreader (IHS)/electromagnetic interference (EMI) shield package and method of manufacturing thereof for reducing warpage

Disclosed is a method of manufacturing a semiconductor device that includes adhering a plurality of semiconductor substrates and a framing member to a supporting surface of a carrier substrate. The semiconductor substrates can be wafers that can be diced or cut into a plurality of dies. Thus, the wafers each have respective active surfaces and at least one respective integrated circuit region. The method can further include encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant. Subsequently, the carrier substrate is removed and a redistribution layer (RDL) is formed on the semiconductor substrates and the framing member.

Multiple wafers fabrication technique on large carrier with warpage control stiffener

Disclosed is a method of manufacturing a semiconductor device that includes molding and curing a framing member having an upper side that defines an array of indentations. Semiconductor dies are then adhered to the framing member within respective indentations. The upper side of the framing member and the dies are covered with an RDL. Formation of the RDL includes deposition of a dielectric material that also fills gaps between the dies and the framing member within the indentations. The framing member can be molded to have a thickness that can provide mechanical strength to resist damage to the dies during the formation of the RDL or other manufacturing processes, for example due to warping of the dies. After the RDL is completed, this excess framing member material can then be removed from lower side of the framing member and the structure can be diced to separate the dies into respective semiconductor devices.

Molded cavity fanout package without using a carrier and method of manufacturing the same

Disclosed is a display module and method of manufacturing the same, where the display module comprises a LCD panel, a driver IC for driving the LCD panel, and a FPC electrically coupled to the driver IC. The LCD panel includes an array of TFT pixels on a TFT array substrate. The TFT array substrate defines a driver cavity in which the driver IC is disposed. The driver IC includes an interface side and an opposing non-interface side. The interface side includes an image signal input pad and a driving signal output pad. The driver IC is configured to receive image signals from the FPC, to process the image signals into drive signals, and to transmit the drive signals to one or more of the plurality of TFT pixels via an RDL electrical connection.

System and method of embedding driver IC (EmDIC) in LCD display substrate

Disclosed is a display module and method of manufacturing the same, where the display module comprises a LCD panel, a driver IC for driving the LCD panel, and a FPC electrically coupled to the driver IC. The LCD panel includes an array of TFT pixels on a TFT array substrate. The TFT array substrate defines a driver cavity and one or more die cavities in which the driver IC and one or more other IC dies are disposed. The driver IC includes an image signal input pad and a driving signal output pad. The driver IC is configured to receive image signals from the FPC, to process the image signals into drive signals, and to transmit the drive signals to TFT pixels via an RDL electrical connection and a through-glass via through the TFT array substrate.

System and method of manufacturing frameless LCD display

An integrated circuit package that includes an integrated circuit die, a redistribution substrate, a wirebond interconnect and a package substrate is disclosed. The redistribution substrate is formed on the integrated circuit die and may be wider than the integrated circuit die. The package substrate is formed below the integrated circuit die. The wirebond interconnect may have one of its ends attached to the redistribution substrate and another end attached to the package substrate. In addition to that, another integrated circuit die may be formed between the redistribution substrate and the package substrate. The integrated circuit dies may communicate with each other through the redistribution substrate. In addition to that, a method to manufacture the integrated circuit package may also be disclosed.

Wafer-level fan-out wirebond packages

An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an integrated circuit die. The second conductive pad may directly contact the first conductive pad on the interposer substrate. The integrated circuit package may further include a package substrate having a cavity, in which the interposer substrate and the integrated circuit are disposed in the cavity. The interposer substrate may include interconnect pathways that are electrically coupled to the first and second conductive pads. A heat spreader may subsequently form over the integrated circuit die and the package substrate.

Bumpless wafer level fan-out package

An interposer is provided. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon substrate layer is formed on top of the glass substrate layer. The interposer may also be known as a hybrid interposer because it includes two different types of substrate layers forming one interposer. The through interposer via is formed to go through the silicon substrate layer and the glass substrate layer. The interposer may be used for forming an integrated circuit package. The integrated circuit package includes multiple integrated circuits that are mounted on the interposer.

Silicon-glass hybrid interposer circuitry

Integrated circuit packages with enhanced thermal conduction are disclosed. A disclosed integrated circuit package includes a package substrate. An integrated circuit die with a layer of metal on its backside is mounted on the package substrate at a first temperature (e.g., reflow temperature). The package further includes a heat spreading lid that is bonded to the integrated circuit die at a second temperature, which is less than the first temperature. The heat spreading lid is formed over the integrated circuit die in which the heat spreading lid makes physical contact with the integrated circuit die via the layer of metal.

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San Jose, CA, United States of America

Minghao Shen