Semiconductor Manufacturing International (Shanghai) Corporation

Mingching Wang

Jin Kang

Kuang-Yu Huang

Yan-Shi Tian

Chi-po Liao

A method for processing integrated circuit devices including forming self aligned contact regions. The method includes providing a partially completed semiconductor wafer, the wafer including one or more semiconductor chips, where each of the chips including a plurality of MOS gate structures. Each of the gate structures is formed on a substrate and having a first layer of silicon nitride formed overlying portions including a contact region between the gate structures. Each of the chips has conformal layer of doped silicon glass of a predetermined thickness overlying the silicon nitride layer and the gate structures. The method then applies a plasma etching process to the doped silicon glass to expose a portion of the first silicon nitride layer using an anisotropic etching component to vertically remove portions of the doped silicon glass. A step of cleaning the exposed portion of silicon nitride using an isotropic component is also included. The method forms a second silicon nitride layer on the exposed portion of the second silicon nitride layer and removes the second silicon nitride layer and exposed portion of the first silicon nitride layer to expose the contract region on the substrate. The method processes the exposed contact region using a soft etching technique.

Method for forming self aligned contacts for integrated circuit devices

A method for processing integrated circuit memory devices. The method includes supporting a partially completed substrate, the substrate comprising a plurality of MOS gate structures. Each of the gate structures has substantially vertical regions that define sides of the gate structures. The method forms a conformal dielectric layer overlying the gate structures. The conformal dielectric layer has a predetermined thickness of material that covers each of the gate structures including vertical regions. The method also forms sidewall spacers on the sides of the gate structures from the conformal dielectric layer using an anisotropic etching process and exposes a portion of the substrate region during the formation of the sidewall spacers using the anisotropic etching process to cause physical damage (e.g., plasma damage, cracks) to a portion of the exposed portion of the substrate. The method smoothes exposed portions of the sidewall spacers and exposed portions of the substrate using at least a plasma treatment process including an isotropic etching component to the exposed portion of the substrate and sidewall spacers on the sides of the gate structures whereupon the exposed portion of the sidewall spacers result to a predetermined surface roughness value.

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Shanghai, China

Mingching Wang