Sj Semiconductor (Jiangyin) Corporation

Mingchih Chen

Chengchung Lin

Yenheng Chen

Jangshen Lin

Hanlung Tsai

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

Wafer-level ASIC 3D integrated substrate, packaging device and preparation method

The present disclosure provides a wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method. The substrate includes a first wiring layer, conductive pillars, a molding layer, a second wiring layer and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer, the first metal wire layer is exposed from a top surface of the first dielectric layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each conductive pillar are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The molding layer molds the conductive pillars. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

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Jiangyin, China

Mingchih Chen