Tetramem Inc.

Mingche Wu

Ning Ge

Minxian Max Zhang

Mingyi Rao

A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

CMOS-compatible resistive random-access memory devices with a via device structure

The present disclosure provides mechanisms for reducing and suppressing random telegraph noise (RTN) for a crossbar circuit. A processing device may perform a programming process to program the conductance of a resistive random-access memory (RRAM) device in the crossbar circuit to a target conductance value. The processing device may then determine whether a random telegraph noise (RTN) value associated with the RRAM device is within a predetermined range of acceptable RTN values. If the RTN value associated with the RRAM device is not within a predetermined range of acceptable RTN values, one or more noise-reduction voltages may be applied to the RRAM device until the RTN value associated with the RRAM device is within the predetermined range of acceptable RTN values.

Suppressing random telegraph noise in crossbar circuits

A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide; a top electrode, and an interface between the switching oxide layer and the top electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfOor TaO, wherein x≤2.0, and wherein y≤2.5. The interface layer comprises a layer of at least one of AlO, MgO, YO, or LaO. The forming-free RRAM device may be switched to multiple resistance levels without a forming process.

Growing community of inventors

San Jose, CA, United States of America

Mingche Wu