Taiwan Semiconductor Manufacturing Comp. Ltd.

Globalfoundries Singapore Pte. Ltd.

Other

Cisco Technology, Inc.

Stmicroelectronics S.r.l.

Stmicroelectronics Asia Pacific Pte Limited

Globalfounders Singapore Pte. Ltd.

Globalfoudnries Singapore Pte. Ltd.

Ming Zhu

Harry-Hak-Lay Chuang

Bao-Ru Young

Lee-Wee Teo

Harry Hak-Lay Chuang

Cheng-Cheng Kuo

Yi-Ren Chen

Hak-Lay Chuang

Pinghui Li

Chi-Wen Liu

Yiang Aun Nga

Hui-Wen Lin

Po-Nien Chen

Han-Guan Chew

Danny Pak-Chum Shum

Wei Cheng Wu

Jin-Aun Ng

Chao-Hsiung Wang

Sheng-Chen Chung

Darin A Chan

Kuo-Cheng Ching

Carlos H Diaz

Eng Huat Toh

Chao-Cheng Chen

Ryan Chia-Jen Chen

Yuan-Sheng Huang

Jyun-Ming Lin

Ting-Hua Hsieh

Sin-Hua Wu

Che-Cheng Chang

Shyue Seng Tan

Kuo-Ji Chen

Chang-Yin Chen

Wanbing Yi

Ming-Hsiang Song

Yi-Jen Chen

Yung-Jung Chang

Ching-Che Tsai

Chung-Hau Fei

Kai-Shyang You

Elgin Kiok Quek

Xinshu Cai

Fan Zhang

Chi-Ju Lee

Haiqing Zhou

Liying Zhang

Su Yi Susan Yeow

Shi Ya Phyllis Lim

Tze-Liang Lee

Wei-Cheng Wu

Chii-Horng Li

Chun-Hung Chen

Susie J Wee

Yen-Ru Lee

Yannick Guedon

Lee Wee Teo

Paolo Angelini

Yajun Zhang

Shunqiang Gong

Chia Ming Liang

Rizhi Chen

Danny PakChum Shum

Aikepaer Abuduweili

Chuin Boon Yeap

Shu Zhong

Chin Fong Lee

Siqi Ling

Bao Ru Young

Boa-Ru Young

Chun Shan Yin

Harry-Hay-Lay Chuang

Weining Cheng

Harry-Hak Lay Chuang

Hui Wen Lin

Disclosed are a system and method for automatically and systematically generating device-based design rules and corresponding device-based design rule checking (DRC) codes. In the system and method, design rules associated with specific devices are generated based on at least one table of related data (e.g., maturity status information, restriction status information, etc.) for different devices. Based on the design rules and on unique definitions for the specific devices, design rule checking (DRC) codes associated with the specific devices are generated. By using this approach, comprehensive and accurate device-based design rules and corresponding device-based DRC codes can be quickly generated to ensure acceptable product reliability and yield. Furthermore, processes used to generate the device-based DRC codes can be iteratively repeated (e.g., when the information used for generating the unique definitions of devices and/or generating the design rules changes) to update the device-based DRC codes and, thereby ensure DRC accuracy.

System and method for automatic generation of device-based design rules and corresponding design rule checking (DRC) codes

A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

Vertical tunneling field-effect transistor cell

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Structure and method for vertical tunneling field effect transistor with leveled source and drain

A semiconductor device includes a substrate with an isolation region surrounding a P-active region and an N-active region, a first gate electrode comprising a first metal composition over the N-active region, and a second gate electrode with a center portion over the P-active region and an endcap portion over the isolation region. The endcap portion includes a first metal composition, and the center portion includes a second metal composition different from the first metal composition, and the center portion and the endcap portion do not overlap. An inner sidewall of the endcap portion is substantially aligned with a sidewall of the isolation region.

Metal gate structure of a CMOS semiconductor device and method of forming the same

A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.

Gate structure of a semiconductor device and method of making

Vertical tunneling field-effect transistor cell and fabricating the same

Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

Memory device with density-controllable dummy fill strategy for near-MRAM  periphery and far-outside-MRAM logic regions for embedded MRAM technology

A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.

High-K film apparatus and method

A method of manufacturing a semiconductor structure includes forming a first dummy strip over a first active region and an isolation region of a substrate, removing a first portion of the first dummy strip from the first active region to form a first opening, filling the first opening with a first metal composition, removing a second portion of the first dummy strip from the isolation region to form a second opening, and filling the second opening with a second metal composition.

Fabrication method of a metal gate structure

Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.

Method and device for embedding flash memory and logic integration in FinFET technology

A method of making a semiconductor device includes etching an insulation layer to form a plurality of openings over a first region of the substrate and a plurality of openings over a second region of the substrate. The method includes filling a first opening of the plurality of openings over the first region with a first P-metal. The method includes filling a second opening of the plurality of openings over the first region with a first N-metal. An area of the first N-metal substantially differs in size from an area of the first P-metal. The method includes filling a first opening of the plurality of openings over the second region with a second P-metal. The method includes filling a second opening of the plurality of openings over the second region with a second N-metal. An area of the second N-metal differs from an area of the second P-metal.

Semiconductor die

A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.

Gate structure of a semiconductor device

Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.

A system, method, and computer-readable storage device configured to display a network topology on a display screen of a computing device. The network topology includes a first group of components in an expanded format and a second group of components in a collapsed format. An input is received that is associated with the second group of components, and is arranged to cause the second group of components to be expanded into the expanded format. Finally, the method includes, based on a parameter and the input, automatically collapsing the first group of components from the expanded format into the collapsed format.

System and method of providing a computer networking tool and interfaces

Growing community of inventors

Singapore, Singapore

Ming Zhu