Imec Vzw

Siltronic Ag

Ming Zhao

Nadine Collaert

Amey Mahadev Walke

Peter Storck

Niamh Waldron

Annelies Delabie

Norbert Werner

Sarad Bahadur Thapa

Weiming Guo

A method for manufacturing a semiconductor structure that comprises providing a monocrystalline silicon base layer comprising a first region for manufacturing the III-N semiconductor device and a second region for manufacturing the silicon semiconductor device; providing on the monocrystalline silicon base layer a mask layer, the mask layer being interrupted, in the first region, by a recess in the monocrystalline silicon base layer, wherein the mask layer comprises a 2D material; forming, selectively, a layer of gamma-AlOat the bottom of the recess by a first growth process; forming, selectively on the layer of gamma-AlO, a III-N semiconductor device stack by a second growth process, and thereafter; manufacturing, in the second region, at least partially a silicon semiconductor device.

Method of manufacturing a semiconductor structure

The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.

Cointegration of gallium nitride and silicon

A method of forming a semiconductor structure for a III-N semiconductor channel device and a device produced by the method are disclosed. The method includes: (i) forming a buffer structure on a Si-substrate, wherein forming the buffer structure includes: forming a superlattice including at least one superlattice block, each superlattice block including a repetitive sequence of superlattice units, each superlattice unit including a first layer and a second layer formed on the first layer, wherein the first layer is a carbon-doped AlGaN layer and the second layer is a carbon-doped AlGaN layer, wherein x and y differ from each other and 0&#x2264;x&#x2264;1, 0&#x2264;y&#x2264;1, and wherein said at least first and second layers are epitaxially grown at a temperature of 980&#xb0; C. or lower, and (ii) forming a III-N semiconductor channel layer above the buffer structure wherein the channel layer is epitaxially grown at a temperature of 1040&#xb0; C. or lower and is grown to a thickness of 1 &#x3bc;m or smaller.

Method for forming a semiconductor structure for a gallium nitride channel device

According to an aspect of the present disclosure, there is provided a III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block and a second superlattice block formed on the first superlattice block, the first superlattice block including a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, the second superlattice block including a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, wherein an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.

Formation of a III-N semiconductor structure

The present disclosure relates to a III-N based substrate for power electronic devices, comprising a base substrate, a III-N laminate above the base substrate and a buffer layer structure between the base substrate and the III-N laminate. The buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate. The first superlattice laminate comprises a repetition of a first superlattice unit which consists of a plurality of first AlGaN layers. The second superlattice laminate comprises a repetition of a second superlattice unit which consists of a plurality of second AlGaN layers. An average aluminum content of the first superlattice laminate is a predetermined difference greater than an average aluminum content of the second superlattice laminate, to improve the vertical breakdown voltage. The present disclosure also relates to a method for manufacturing a III-N based substrate for power electronic devices.

III-N based substrate for power electronic devices and method for manufacturing same

A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the &#x3c;111&#x3e;-direction toward the &#x3c;11-2&#x3e;-direction by an angle &#x3b8; of not less than 0.3&#xb0; and not more than 6&#xb0;, the azimuthal tolerance of the inclination being &#xb1;0.1&#xb0;; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlGaN layers, wherein 0&#x3c;&#xd7;&#x3c;1.

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Bertem, Belgium

Ming Zhao