Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Zhang Kuo

Cheng-Chung Lin

Sang Hoo Dhong

Chung-Cheng Chou

Osamu Takahashi

Ping-Lin Yang

Hank Cheng

Ho-Chieh Hsieh

Lee-Chung Lu

Ta-Pen Guo

Subramani Kengeri

Bharath Upputuri

Pey-Huey Chen

Kuo Feng Tseng

Jimmy Hsiao

Hui-Zhong Zhuang

Li-Chun Tien

Chih-Chiang Chang

Shang-Chih Hsieh

Chiting Cheng

Yi-Tzu Chen

Chia-Wei Su

Jen-Hang Yang

Jia-Rong Hsu

Sang Hoo Dong

Kuo-Feng Tseng

Hsiu-Feng Peng

Sang-Hoo Dhong

According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a source side and a drain side; providing a place-and-route boundary (prBoundary) of the first cell based on the configuration of the two sides of the first cell; providing a second cell having two sides, each side configured as at least one of a source side and a drain side; providing a prBoundary of the second cell based on the configuration of the two sides of the second cell; and placing the first cell and the second cell based on the prBoundary of the first cell and the prBoundary of the second cell.

Method for cell placement in semiconductor layout and system thereof

An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Integrated circuit with well and substrate contacts

One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.

Scan cell assignment

An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.

Electron beam lithography methods including time division multiplex loading

A clock regenerator includes a pulse generating module, a control logic module, a gating module and an output module. The pulse generating module is configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal. The control logic module is configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals. The gating module is configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal. The output module is configured to provide a local clock signal according to the intermediate clock signal.

Clock regenerator

A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.

Memory circuit for pre-charging and write driving

A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the mirror array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature.

Charged particle lithography system with a long shape illumination beam

The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.

Electron beam lithography systems and methods including time division multiplex loading

The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Memory building blocks and memory design using automatic design tools

A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.

Adaptive write bit line and word line adjusting mechanism for memory

Among other things, one or more techniques for conditional cell placement are provided herein. In an embodiment, a conditional boundary is created for a first cell. For example, the conditional boundary enables the first cell to be placed relative to a second cell based on a conditional placement rule. In an embodiment, the first cell is placed in a first manner relative to the second cell based in a first scenario. In a second scenario, different than the first scenario, the first cell is placed in a second manner relative to the second cell. In this manner, conditional cell placement is provided, thus providing flexibility and improved layout efficiency with regard to semiconductor fabrication, for example.

Conditional cell placement

A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.

Pulse generator

A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time.

Memory with word-line segment access

A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.

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Xigang Shiang, Taiwan

Ming-Zhang Kuo