Realtek Semiconductor Inc.

Ming-Yuh Yeh

Der-Zheng Liu

Yen-Chung Chen

Chen-Chih Huang

Kuang-Yu Yen

Chung-Yao Chang

Tay-Her Tsaur

Chi-Shun Weng

Meng-Han Hsieh

Ming-Je Li

Yu-Jen Lin

Wei-Ren Hsu

Chin-Wen Huang

Yi-Ting Wei

Fu-Hsin Chen

Kai-Yi Fang

Yun-Jan Hong

Tzu-Yu Chao

Chen-Chun Fan

A storage device includes a controller and a memory. A method of storage space management for the storage device is executed to perform steps as below. The controller calculates an expectedly used capacity and an effective capacity of the memory. The controller determines whether blocks of the memory include one or more blocks that are non-bad blocks and are prohibited from reading/writing. When the one or more blocks are determined to be non-bad blocks and to be prohibited from reading/writing, the controller marks each of the one or more blocks as a restricted block other than a bad block, thereby maintaining the effective capacity to be unchanged. The controller compares difference of the effective capacity and a total capacity of the one or more blocks that are marked as the restricted block to the expectedly used capacity to determine whether to prohibit programming to the memory.

Method of storage space management for improving endurance of storage devices

A data processing method includes: configuring a predetermined memory space to record information regarding data to be backed up of a memory device, where the information is used to indicate data associated to which logical memory space is the data to be backed up; and updating the information according to commands received from a host device.

Data processing method and memory controller utilizing the same

The present disclosure provides a network master device and a network communication method for realizing a cooperative service set, in which the network master device and the network communication method are capable of controlling wireless serving devices to have them keep wireless connections with a wireless terminal device concurrently. An embodiment of the network master device includes a control circuit configured to execute the following steps: receiving uplink packets come from wireless serving devices respectively, and transmitting a transmission packet to an external network according to at least one of the uplink packets, in which a source address of each of the uplink packets is an address of a wireless terminal device; and transmitting at least one downlink packet to at least one of the wireless serving devices, in which a destination address of each the downlink packet is the address of the wireless terminal device.

Network master device and network communication method for realizing cooperative service set

The present invention discloses a wireless communication device including: a transmission circuit generating a digital modulation signal according to transmission data, and analogizing the digital modulation signal to generate and transmit a transmission signal in a first mode; a reception circuit receiving a reception signal including an interference component caused by the transmission circuit; a self-interference cancellation circuit being enabled in the first mode and disabled in a second mode, providing an analog self-interference cancellation signal for the wireless reception circuit according to the transmission signal to cancel a part of the interference component, and providing a digital self-interference cancellation signal for the reception circuit according to the digital modulation signal to cancel another part of the interference component; and a control circuit having the wireless communication device operate in one of the first mode and the second mode according to at least one of indices and parameters.

Wireless communication device and control method

An integrated circuit is disclosed, including at least one configuration pin, an interface circuit, a detecting circuit, a determining circuit and a storage unit. A physical layer circuit of the invention not only increases the flexibility of setting PHY addresses, but also reduces the number of configuration pins.

Circuit and method for setting data and their application to integrated circuit

The present invention discloses a microphone detection circuit for detecting whether an external device includes a microphone. The microphone detection circuit comprises: an audio circuit for receiving an analog input signal which is a signal from the external device or a preset signal. The audio circuit comprises: an analog-to-digital conversion unit to generate a digital audio signal according to the analog input signal; a decision unit, coupled to the analog-to-digital conversion unit, to determine whether the digital audio signal satisfies a predetermined threshold to thereby generate an analysis result, wherein if the digital audio signal satisfies the predetermined threshold, the analysis result indicates that the external device includes a microphone; and a control unit, coupled to the decision unit, to control an operation of the audio circuit according to the analysis result.

Microphone detection and selection circuit and method

A wireless communication device is disclosed. The wireless communication device includes a frequency hopping communication circuit, a power spectral density circuit and a control circuit. The frequency hopping communication circuit includes a channel map. The frequency hopping communication circuit selects one of channel in a channel map to connect to another frequency hopping communication circuit according to the channel map. The power spectral density circuit for generating a power spectral density signal by measuring spectrums on all channels connected to the frequency hopping communication circuit. The control circuit receives the power spectral density and output statistical distribution data to the frequency hopping communication circuit. The frequency hopping communication circuit updates the channel map according to the statistical distribution data.

Method and device for implementation of adaptive frequency hopping by power spectral density

An oscillator and the control method thereof. The oscillator includes an oscillation unit to receive a first current and to generate an oscillating signal according to the first current, a frequency-to-voltage converter to receive the oscillating signal and to generate a converted voltage according to a frequency of the oscillating signal, and a voltage-to-current converter to receive the converted voltage and to generate the first current according to the converted voltage, wherein the first current is modulated from a first value to a second value after the initiation of the oscillation unit.

Oscillator and control method thereof

The invention discloses a single network interface device with multi-ports, the network interface device supports two or more physical network transmission routes to transmit and receive data, and upload the received data into a host through a host interface or download the data waiting to be transmitted to network from the host through the host interface. Therefore, the present invention increases network communication speed and improves host interface bandwidth.

Single network interface circuit with multiple-ports and method thereof

A transmission line driver for generating an output signal to drive a transmission line is disclosed. The transmission line driver includes a voltage driver and a current driver. The voltage driver generates a voltage signal to drive the transmission line. The current driver generates a current signal to drive the transmission line. The amplitude of the output signal is determined according to the voltage signal and/or the current signal.

Transmission line driver

A configured setting circuit and method thereof is disclosed. The configured setting circuit includes a multi-phase clock generator, a plurality of terminals, and a decision circuit. The multi-phase clock generator generates a plurality of multi-phase signals with different phases to be outputted via the terminals. The decision circuit detects a phase difference between the input signal and the reference signal and outputs a configuration data according to the phase difference between the input signal and the reference signal.

Circuit and method for reducing pin count of chip

A voltage jitter suppression circuit and a method thereof are disclosed. The circuit is utilized for alleviating the voltage jitter phenomenon of an IC. Regardless of the circuit frequency and voltage, the voltage jitter phenomenon of the circuit can be improved significantly by utilizing the present invention.

Growing community of inventors

Taipei, Taiwan

Ming-Yuh Yeh