Mstar Semiconductor, Inc.

Mediatek Corporation

Ming-Yu Hsieh

Shih-Chieh Yen

Yao-Chi Wang

Khurram Muhammad

Chih-Ming Hung

Sheng-Che Tseng

Pou-Chi Chang

Pei-Kai Liao

James Han Wang

Chi-Hsueh Wang

Bernard Ginetti

Dennis Mahoney

Zhongxuan Zhang

Yi Wei Lu

Jian-Yu Ding

Hsu-Hung Chang

Hsin-Ying Lee

Yu-Lin Hsieh

Jen-Kuei Tsai

Po-Yang Chang

Tzu-Chin Lin

A wireless communication device includes a first wireless communication system and a second wireless communication system. Regarding the first wireless communication system, an up-conversion circuit up-converts a first transmit (TX) signal in a baseband to generate a second TX signal with a first carrier frequency, and a front-end circuit transmits the second TX signal to another wireless communication device. Regarding the second wireless communication system, a first down-conversion circuit down-converts a first receive (RX) signal with a second carrier frequency to generate a second RX signal with a third carrier frequency, and a second down-conversion circuit down-converts the second RX signal with the third carrier frequency to generate a third RX signal in the baseband. The third carrier frequency is different from all fundamental frequencies included in a band combination that is employed at the first wireless communication system and is supported by another wireless communication device.

Wireless communication device with frequency planning for spur avoidance under coexistence of multiple wireless communication systems

Aspects of the disclosure provide a control apparatus that includes transceiver circuitry and processing circuitry. The transceiver circuitry is configured to transmit/receive signals from a plurality of terminal devices using a shared channel. The processing circuitry is configured to determine distances to the plurality of terminal devices, allocate resource elements in the shared channel according to the distances, and communicate, via the transceiver circuitry, with the plurality of terminal devices according to the allocation of the resource elements in the shared channel.

Method and apparatus for network scheduling

A communication circuit includes a receiver path, a frequency translating loop filter and a signal source circuit. The frequency translating loop filter includes an auxiliary mixer, and a frequency translating filter backend circuit such as a filter. The signal source circuit can be shared with a transmitter path. When the receiver path receives an external signal, the auxiliary mixer and the frequency translating filter backend circuit perform high-frequency filtering. When the receiver path need not receive the external signal, the auxiliary mixer up-converts a low-frequency auxiliary signal provided by the signal source circuit to a high-frequency domain, and the up-converted signal is received by the receiver path. Thus, an operation parameter of the receiver path can be adjusted and calibrated according to a response of the receiver path.

Communication circuit and associated calibration method

A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve.

Frequency calibration apparatus of phase locked loop and method thereof

A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration.

Reconfigurable circuit block supporting different interconnection configurations for rate-conversion circuit and processing circuit and related method thereof

A transmitter system includes a digital phase rotator, a phase rotation controller, and a digital radio-frequency (RF) transmitter. The digital phase rotator receives a first constellation data, and applies a digital phase rotation to the received first constellation data to generate a second constellation data. The phase rotation controller configures the digital phase rotation. The digital RF transmitter receives a digital input data derived from the second constellation data, and converts the digital input data into an analog RF output.

Transmitter system with digital phase rotator used for applying digital phase rotation to constellation data and related signal transmission method thereof

A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.

Communication system and sample rate converter thereof

A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal.

Frequency multiplier and associated method

A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

Multiplexed configurable sigma delta modulators for noise shaping in a 25-percent duty cycle digital transmitter

An edge alignment apparatus includes: a signal source, for generating a first and a second square wave signals; a phase delay circuit, for receiving the first and the second square wave signals to generate a delayed first and a delayed second square wave signals; a data circuit, for generating a third square wave signal according to the delayed second square wave signal; and a phase calibrating circuit, for receiving the third square wave signal and the delayed first squared wave signal to generate at least one phase tuning signal to the phase delay circuit for tuning a phase difference between the delayed first and the delayed second square wave signals, such that a signal edge of the third square wave signal aligns with that of the first square wave signal. The first, second and third square wave signals have a same frequency.

Method and associated apparatus for clock-data edge alignment

An offset phase-locked loop (PLL) transmitter comprises a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts the operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value.

Offset phase-locked loop transmitter and method thereof

A voltage-controlled oscillator (VCO) control circuit, used for controlling a VCO to process phase locking procedure after receiving a frequency locking signal, comprises an operating frequency controller and a judgment unit. The operating frequency controller, coupled to the VCO and the judgment unit, generates one of a first control code and a second control code to the VCO. The judgment unit, coupled to an input end of the VCO, generates a phase locking signal according to a voltage control signal inputted to the VCO. When the operating frequency controller receives the frequency locking signal, the operating frequency controller generates a first control code to control the VCO to switch from a first candidate VCO curve to a second candidate VCO curve. When the operating frequency controller receives the phase locking signal, the operating frequency controller generates a second control code to control the VCO to switch from the second candidate VCO curve to the first candidate VCO curve.

VCO control circuit and method thereof, fast locking PLL and method for fast locking PLL

A phase-locked loop (PLL) including an active filter, a voltage-controlled oscillator (VCO), two phase detectors, a charge pump and a digital-to-analog converter (DAC) is provided. The VCO generates an oscillation signal according to a control signal provided at an output of the active filter. The first phase detector generates a phase difference signal according to a reference signal and a feedback signal associating with the oscillation signal. The charge pump provides a charging current to a first input of the active filter according to the phase difference. The second phase detector generates a digital reference signal according to the phase difference between the reference signal and the feedback signal. The DAC converts the digital reference signal to an analog reference voltage and provides the analog reference voltage to the second input of the active filter.

Phase-locked loop

A phase-locked loop (PLL) includes a charge pump, a frequency divider, a voltage detector, a control module, and a calibration module. When a predetermined current amount and a predetermined frequency dividing amount are provided, the voltage detector measures a voltage associated with an output frequency of the PLL to generate a first reference voltage. When a test current amount and the predetermined frequency dividing amount are provided, the voltage detector again measures the voltage to generate a second reference voltage. When the predetermined current amount and a test frequency dividing amount are provided, the voltage detector again measures the voltage to generate a third reference voltage. The control module estimates a loop gain of the PLL according to the current amounts, the frequency dividing amounts and the reference voltages. The calibration module calibrates the PLL according to the loop gain.

Phase-locked loop with calibration function and associated calibration method

A circuit for calibrating the DC offset in a wireless communication device utilizes a voltage-generating circuit to generate a first voltage value and its negative value, and utilizes a detecting circuit to detect an output of the wireless communication device and generate a first target-branch reference value corresponding to the power of the output when the first voltage value is inputted into a target branch (e.g., the in-phase branch or the quadrature branch) of the wireless communication device, and detect an output of the wireless communication device and generate a second target-branch reference value corresponding to the power of the output when the negative value of the first voltage value is input into the target branch. Then, an estimating circuit estimates the DC offset on the target branch according to the first and second target-branch reference values and the first voltage value.

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Hsinchu Hsien, Taiwan

Ming-Yu Hsieh