Advanced Micro Devices Corporation

Ming Yin Hao

Emi Ishida

Effiong Etukudo Ibok

Richard P Rouse

Srinath Krishnan

Srinath Krishman

Deepak K Nayak

Zicheng Gary Ling

Asim A Selcuk

Submicron-dimensioned, MOSFET devices are formed using multiple implants for forming an impurity concentration distribution profile exhibiting three impurity concentration peaks at a predetermined depths below the semiconductor surface substrate. The inventive method reduces &ldquo;latch-up&rdquo; and &ldquo;punch-through&rdquo; with controllable adjustment of the threshold voltage.

Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through

Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.

Oxygen implantation for reduction of junction capacitance in MOS transistors

Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

MOS transistor processing utilizing UV-nitride removable spacer and HF etch

Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its deposition, e.g., by ion implantation, to augment its etch rate with a room temperature etchant, e.g., dilute aqueous HF. The treated spacers are removed with the dilute, aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Removable spacer technology using ion implantation to augment etch rate differences of spacer materials

Submicron-dimensioned, p-channel MOS transistors and CMOS devices a formed using nitrogen and boron co-implants for forming p-type well regions, each implant having a parabolically-shaped concentration distribution profile. During subsequent thermal annealling, boron-doped wells are formed, each having a retrograde-shaped concentration distribution profile exhibiting a peak boron concentration at a preselected depth below the semiconductor substrate surface. The inventive method reduces &ldquo;short-channel&rdquo; effects such as &ldquo;punch-through&rdquo; while maintaining high channel mobility.

Retrograde well structure formation by nitrogen implantation

Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for &ldquo;latch up&rdquo; are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate insulator layer.

Indium retrograde channel doping for improved gate oxide reliability

Sub-micron-dimensioned, asymmetrically-configured MOS and/or CMOS transistors are fabricated using removable sidewall spacers made of a material, such as UV-nitride, one of which is selectively treated subsequent to deposition, e.g., by ion implantation, to augment the etch rate thereof with a room temperature etchant, e.g., dilute aqueous HF. The treated spacer is removed with the dilute, aqueous HF prior to implantation of asymmetrically-configured, moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Removable spacer technology using ion implantation for forming asymmetric MOS transistors

Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of heavily-sloped source/drain junction regions but prior to annealing of the implant for dopant diffusion/activation and lattice damage relaxation. Lightly-or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch

Submicron-dimensioned devices are formed whereby a desired relationship between the impurity concentration peak and a lightly doped source/drain region is obtained.

Method for fabricating semiconductor device

CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type transistor shallow source/drain implants; forming relatively thin first sidewall spacers on the gates of both transistors; ion implanting a P-type impurity, e.g. BF,, to form shallow source/drain extension implants for the P-type transistor; forming relatively thick side wall spacers on the first sidewall spacers of both transistors; ion implanting, e.g. As, to form moderately or heavily doped N-type implants; activation annealing at a first temperature, e.g., about 1050&deg; C. to form the shallow N- and P-type source/drain extensions and moderately or heavily doped P-type source/drain regions; ion implanting a P-type impurity, e.g., BF,, to form moderately or heavily doped P-type source/drain implants; and activation annealing at a second temperature less than the first temperature, e.g., at about 1000&deg; C. to form moderately or heavily doped P type source/drain regions.

Growing community of inventors

Sunnyvale, CA, United States of America

Ming Yin Hao