Advanced Micro Devices Corporation

Ming-Yin Hao

Deepak K Nayak

Rajat Rakkhit

Derick J Wristers

Emi Ishida

Robert Bertram Ogle, Jr

Marina V Plat

Witold P Maszara

Srinath Krishnan

David S Bang

A semiconductor device having a retrograde channel profile is achieved by forming a retrograde impurity region in the surface portion of a semiconductor substrate, and subsequently forming a semiconductor layer on the retrograde impurity region at a predetermined thickness. The thickness of the semiconductor layer is controlled to localize the retrograde impurity region and its impurity concentration peak at a predetermined depth, thereby reducing the device's susceptibility to &ldquo;reverse short channel effects.&rdquo;

Laser tailoring retrograde channel profile in surfaces

Short channel effects are curtailed thereby increasing integrated circuit speed by forming a channel dopant with an asymmetric impurity concentration profile. Embodiments include ion implanting Si or Ge at a large tilt angle to amorphize a portion of a designated channel region with a varying degree of amorphization decreasing from the intended drain region to the intended source region, substantially vertically ion implanting channel dopant impurities and annealing. During annealing, diffusion is retarded in areas of increased amorphization, thereby forming an asymmetric impurity concentration gradient across the channel region increasing in the direction of the source region.

Semiconductor device with asymmetric channel dopant profile

A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection with the implantation of a conventional n-type dopant (e.g. arsenic or phosphorus), results in a transistor having low series resistance, reduced hot carrier effects and no significant increase in source/drain extension overlap.

Method for making transistor having reduced series resistance

A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided. A self-aligned doping process is used in which the polysilicon gate, the source region, and the drain region, are simultaneously implanted to dopant concentrations of between 1&times;10,and 5&times;10,atoms/cm,.

Method of improving MOS device performance by controlling degree of depletion in the gate electrode

A process for growing an ultra-thin dielelctric layer for use as a MOSFET gate or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density electron traps, and impedes dopant impurity diffusion from/to the dielelctric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Process for reliable ultrathin oxynitride formation

A method of forming a retrograde channel concentration profile in the NMOS region of a semiconductor device and forming a shallow LDD regions in a PMOS region of the semiconductor device. The retrograde channel concentration profile in the NMOS regions is formed by implanting nitrogen and boron ions into the NMOS region at selected concentrations and implantation energy levels. The nitrogen ions are implanted in the NMOS region at a selected concentration in the range of 1&times;10,to 2&times;10,ions per cm,and at a selected implantation energy in the range of 10-100 KeV. The boron ions are implanted in the NMOS region at a selected concentration in the range of 1&times;10,to 1&times;10,ions per cm,and at a selected implantation energy in the range of 5-50 KeV. The shallow LDD regions in the PMOS region are formed by implanting nitrogen and boron ions into the PMOS region at selected concentrations and implantation energy levels. The nitrogen ions are implanted in the PMOS region at a selected concentration in the range of 1&times;10,to 2&times;10,ions per cm,and at a selected implantation energy in the range of 5-50 Kev. The boron ions are implanted in the PMOS region in a selected concentration in the range of 1&times;10,to 5&times;10,ions per cm,and at a selected implantation energy in the range of 10-20 KeV.

Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants

A practical photolithographic process for use in manufacturing isolation structures in semiconductor substrates at the 0.18 &mgr;m scale uses an inorganic anti-reflective coating (ARC) layer, particularly silicon oxynitride, under a silicon nitride mask layer to minimize substrate reflectivity. The same ARC layer increases latitude in process conditions in photolithographic patterning of both a first mask layer and a second planarization mask level. The silicon oxynitride layer additionally reduces edge/corner stress in isolation structures, improving gate oxide integrity in the device of which the isolation structure forms a part. Furthermore, because silicon oxynitride and silicon nitride respond to the same process conditions, a silicon oxynitride ARC layer can be introduced without increasing process complexity.

Minimization of line width variation in photolithography

A CMOS device and a method for forming the same is provided so as to overcome the problem of boron penetration through the thin gate oxide of P-channel devices. Silicon is implanted into the polysilicon gate electrode of the PMOS device functioning as a diffusion barrier for preventing boron penetration through the thin gate oxide and into the semiconductor substrate. As a result, the reliability of the CMOS device will be enhanced.

Preventing boron penetration through thin gate oxide of P-channel

A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Ultrathin oxynitride structure and process for VLSI applications

A method to monitor boron penetration and optimize process parameters in the fabrication of a semiconductor device have an n.sup.+ or a p.sup.- -polysilicon gate. The charge-to-breakdown Q.sub.BD value is used to monitor the boron penetration into the polysilicon/gate oxide interface. Values of Q.sub.BD for various values of process parameters are determined and optimized values for these process parameters are derived.

Method to optimize p-channel CMOS ICs using Q.sub.bd as a monitor of

A method of manufacturing a semiconductor device with reduced hot-carrier induced degradation wherein a nitrogen species is introduced into the gate oxide layer. The introduction of the nitrogen species may be done after the gate etch, after the spacer material deposition, or after the spacer etch. The nitrogen species may also be introduced into the gate oxide after both the gate etch and the spacer material deposition or after both the gate etch and the spacer etch or after all three steps.

Hot-carrier reliability in submicron MOS devices by oxynitridation

A method and circuit for detecting boron at an interface between a p-type polysilicon gate and silicon dioxide gate dielectric is provided. A V.sub.t fluence test using about -6.67 mA/cm.sup.2 is used to detect boron at the interface. A p-channel metal oxide semiconductor ('PMOS') device having a source, drain, substrate, gate and silicon dioxide layer are connected to ground and a current source in order to detect the boron. An about -6.67 mA/cm.sup.2 current is applied to the PMOS gate while the source, substrate and drain are grounded. Various changes in threshold voltages are observed over different stress times. The boron concentration at the polysilicon/gate dielectric interface has been detected by the shift in threshold voltage. The concentration of boron at the interface has been found to degrade oxide quality as evidenced by charge-to-breakdown ('Q.sub.BD ') test of the oxide.

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Sunnyvale, CA, United States of America

Ming-Yin Hao