Triquint Semiconductor Corporation

Lockheed Martin Corporation

Texas Instruments Corporation

Ming-Yih Kao

Edward A Beam, Iii

Kevin L Robinson

Paul Saunier

Larry Charles Witkowski

Gary Alan Evans

Hua Q Tserng

Jinqiao Xie

William H Davenport

Andy Turudic

Hua-Quen Tserng

David Michael Fanning

Walter Anthony Wohlmuth

John Neal Randall

Embodiments include apparatuses and methods related to an HFET. In embodiments, one or all of the buffer layer, the back-barrier layer, or the barrier layer may be formed of a digital alloy. In embodiments, the digital alloy may include alternating layers of alloys of aluminum, gallium, and nitrogen. Other embodiments may be disclosed or claimed herein.

Digital alloy layer in a III-nitrade based heterojunction field effect transistor

A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Method for fabrication of devices in a multi-layer structure

A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same

A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is formed on the spacer layer. The channel layer may be of uniform composition, or may be made from two or more sublayers. A Schottky layer is formed over the channel layer, and source and drain contacts are formed on the Schottky layer. The substrate may be gallium arsenide, indium phosphide, or other suitable material, and the various semiconductor layers formed over the substrate contain indium. The transistor's transition frequency of the transistor is above 200 GHz.

Heterostructure field effect transistor

A light-emitting device includes a GaAs substrate, a light-emitting structure disposed above the substrate and capable of emitting light having a wavelength of about 1.3 microns to about 1.55 microns, and a buffer layer disposed between the substrate and the light-emitting structure. The composition of the buffer layer varies through the buffer layer such that a lattice constant of the buffer layer grades from a lattice constant approximately equal to a lattice constant of the substrate to a lattice constant approximately equal to a lattice constant of the light-emitting structure. The light-emitting device exhibits improved mechanical, electrical, thermal, and optical properties compared to similar light-emitting devices grown on InP substrates.

Long wavelength laser diodes on metamorphic buffer modified gallium arsenide wafers

A novel micro-electro-mechanical (MEMS) RF switch having a cavity (32) in a substrate (28) which creates a spacing between a conductive membrane (34) and a bottom electrode (38). The invention eliminates the need for the dielectric posts found in prior art MEMS RF switches, includes a flexure structure (36) in the membrane (34) which will reduce the required pull down voltage for the membrane, and reduces the stress and fatigue in the membrane due to switch activation.

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Dallas, TX, United States of America

Ming-Yih Kao