Taiwan Semiconductor Manufacturing Comp. Ltd.

Advanced Optoelectronic Technology, Inc.

Network Performance Research Group LLC

Ming-Yi Lin

Kun-Ming Huang

Yen-Sen Wang

Long-Shih Lin

Cheng-Chi Chuang

Fu-Hsiung Yang

Hsuan-Hui Hung

Chen-Hung Lu

Jyh-Kang Ting

Po-Tao Chu

Ming-Tai Chung

Yu-Cheng Yeh

Paul Chu

Ken-Hsien Hsieh

Tai-I Yang

Jyh-Huei Chen

Kun Ting Tsai

Yu-Hsien Lin

Ting Yu Chen

Jui-Chun Weng

Wen-Cheng Chien

Hong-Seng Shue

Chun-Hung Huang

Yuh-Hwa Chang

Chen-Peng Fan

Chie-Iuan Lin

Li-Ming Huang

Chie-luan Lin

Yung-Jui Chen

Peter Hong

Wen-Chen Hung

Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes receiving an integrated circuit layout, inserting, into the integrated circuit layout, a design containing a first set of Front-End Of Line (FEOL) shapes of an integrated circuit and a first set of Back-End Of Line (BEOL) shapes of the integrated circuit, inserting, into the integrated circuit layout, a set of cells containing a second set of FEOL shapes of the integrated circuit and a second set of BEOL shapes of the integrated circuit, removing a subset of the second set of BEOL shapes that conflict with the design, and providing the integrated circuit layout that includes the design and the set of cells for fabrication of the integrated circuit. The second set of FEOL shapes includes contact shapes that define contacts of the integrated circuit.

Integrated circuit layouts with fill feature shapes

Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes initializing a layout for fabricating an integrated circuit. A plurality of fill cells is inserted into the layout. The plurality of fill cells includes a plurality of fill line shapes that correspond to conductive lines of the integrated circuit. Thereafter, a design is inserted into the layout that includes a plurality of functional shapes. A conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality functional shapes are removed. The layout that includes the plurality of fill cells and the design is provided for fabricating the integrated circuit.

A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.

Passivation structure and method of making the same

A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.

Method for forming a multiple layer epitaxial layer on a wafer

A method of fabricating a transistor includes doping non-overlapping first, second, and third wells in a silicon layer of a substrate. The substrate, second and third wells have a first type of conductivity and the first well and silicon layer have a second type of conductivity. First and second insulating layers are thermally grown over the second well between the first well and the third well, and over the third well, respectively. A gate stack is formed over the first insulating layer and the third well. A first source region having the second type of conductivity is formed in the third well. A gate spacer is formed, a fourth well having the first type of conductivity is doped in the third well between the second insulating layer and the gate spacer, a second source region is formed over the fourth well, and a drain is formed in the first well.

Method of fabricating a lateral insulated gate bipolar transistor

The present invention relates to wireless networks and more specifically directed to providing or acquiring an exemplary country code identifier or regulatory domain for a non-limiting device operating in a reduced functionality radio frequency (regulatory) mode based on exemplary location factors and exemplary confidence rankings. One embodiment includes an exemplary regulatory domain selection component configured to weigh location factors associated with a device, based on reliability associated with the location factors, and configured to determine an overall confidence of a country code identifier or a regulatory domain for the device. Another embodiment includes a device configured to operate in a reduced functionality radio frequency (regulatory) or world-wide compliant mode until a regulatory domain can be determined through a trusted cloud service which can be configured to weigh one or more location factors or data sources to facilitate providing or acquiring an exemplary country code identifier or regulatory domain for the device.

System, method, and apparatus for setting a regulatory operating mode of a device

Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

Partial SOI on power device for breakdown voltage improvement

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal connect over and connected to a first active region, over and connected to a second active region and over a shallow trench isolation (STI) region thereby connecting the first active region to the second active region. A metal contact is over and connected to a gate in the STI region. The metal connect is formed in a first opening and the metal contact is formed in a second opening, where the first opening and the second opening are formed concurrently using a single mask. The semiconductor arrangement formed using a single mask is less expensive to fabricate and requires fewer etching operations than a semiconductor arrangement formed using multiple masks.

Semiconductor arrangement and formation thereof

Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.

Cut mask design layers to provide compact cell height

Some embodiments relate to a method of hierarchical layout design, comprising forming a layout of an integrated circuit (IC) according to a design rule that specifies a minimum design rule distance between a neighboring layout features within the IC. Forming the layout comprises forming first and second standard cells having first and second layout features, respectively, that about one-another so that a distance between the first and second layout features is less than the minimum design rule distance. The method further comprises configuring design rule checking (DRC) to ignore this fail. Instead, the layout is modified with an automated layout tool by merging the first and second layout features, or by removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance.

Cell boundary layout

Multiple layer substrate

Methods and apparatus for MEMS release are disclosed. A method is described including providing a substrate including at least one MEMS device supported by a sacrificial layer; performing an etch in solution to remove the sacrificial layer from at least one MEMS device; immersing the substrate including the at least one MEMS device in an organic solvent; and while the substrate is immersed in the organic solvent, removing water from the organic solvent until the water remaining in the organic solvent is less than a predetermined threshold. An apparatus is disclosed for performing the methods. Additional alternative methods are disclosed.

Methods and apparatus for MEMS structure release

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Hsinchu, Taiwan

Ming-Yi Lin