Lsi Logic Corporation

Lsi Corporation

Ming-Yi Lee

Arvind Kamath

Venkatesh P Gopinath

Mohammad R Mirabedini

Chien-Hwa Chang

Helmut Puchner

Samuel Vance Dunton

Jayanthi Pallinti

Dawn M Lee

Weidan Li

Kaijun Leo Zhang

Wilbur C Catabay

Brian A Baylis

Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.

Method characterizing materials for a trench isolation structure having low trench parasitic capacitance

Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

Shallow trench isolation structure with low trench parasitic capacitance

Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance

A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.

Hard mask removal

A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.

Composite spacer scheme with low overlapped parasitic capacitance

Provided is a process for forming a semiconductor device having salicided contacts. A concentration of metal is formed at the substrate surface by exposing the substrate to a metal plasma. The concentration of metal is then annealed to produce a salicided contact. In a separate embodiment, the metallization plasma and salicide anneal occur in-situ in one process step.

Fabrication of metal contacts for deep-submicron technologies

A method for blocking formation of a reacted metal layer on a structure in an integrated circuit. The integrated circuit has a source region, a drain region, a gate, an isolation area formed of a material, and a protective layer formed of substantially the same material as the isolation area. The protective layer overlies at least the source region and the drain region. The method is accomplished while reducing an amount of the material of the isolation area that is removed when the material of the protective layer is removed. A blocking layer is deposited on the integrated circuit. The blocking layer is formed of a material that is substantially different from the material of the isolation area and the protective layer. The blocking layer is patterned to selectively cover portions of the blocking layers that overlie at least the structure and selectively expose portions of the blocking layer that overlie at least the source region, the drain region, and the gate. The exposed portions of the blocking layer are etched with an etchant to substantially remove the exposed portions of the blocking layer, and to expose portions of the protective layer. The etchant etches the blocking layer at a substantially greater rate than the protective layer. The exposed portions of the protective layer are etched for a period of time that is just sufficient to remove the exposed portions of the protective layer, but not sufficient to substantially remove any of the material of the isolation area. Portions of the integrated circuit are thereby exposed, including at least the source region, the drain region, and the gate. Metal is deposited on the exposed portions of the integrated circuit. The metal is reacted with at least the source region, the drain region, and the gate to form the reacted metal layer, and unreacted metal is removed from other exposed portions of the integrated circuit and the blocking layer.

Deep submicron silicide blocking

A process-is disclosed for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where said trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as a stop layer in a CMP process to remove metal; and using this ARC layer as a stop layer to assist in removal of excess metal used to fill trenches and/or vias formed in the oxide layer. The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process to remove metal, than does the underlying oxide dielectric layer. Trenches and/or vias are formed through the ARC layer and the oxide dielectric layer. These trenches and/or vias are then filled by depositing at least one metal layer over the ARC layer. Excess trench and/or via filler metal is then removed from the top surface of the ARC layer by subjecting the metal to a CMP step which is selective to the ARC layer, thereby permitting the ARC layer to function as a CMP stop layer which protects the underlying oxide dielectric layer from exposure to the CMP process. Since the ARC layer has a lower etch rate, in the CMP process to remove metal, than does the oxide dielectric layer, the formation of dished or concave regions in the surface is inhibited, including those regions where the trenches and/or vias are closely spaced apart.

Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure

A method for planarizing an integrated circuit. The integrated circuit is to be planarized to an upper surface using chemical mechanical polishing. The upper surface of the integrated circuit includes regions of a first material and regions of a second material. The first material has a first polishing rate and desired chemical, physical, and electrical properties. The second material has a second polishing rate and desired chemical, physical, and electrical properties. The first polishing rate is greater than the second polishing rate. The regions of the first material adjoin the regions of the second material at interfaces. The upper surface of the integrated circuit is overlaid with a top layer of the second material, that is to be removed by the chemical mechanical polishing. Both the regions of the second material and the top layer of the second material are deposited during a deposition. The upper surface of the integrated circuit tends to form deleterious tapers at the interfaces between the first material and the second material when the chemical mechanical polishing is taken past a desired end point. The improvement comprises modifying the second material to increase the second polishing rate by adding a dopant to the second material prior to planarizing the integrated circuit. The dopant does not significantly adversely affect either the desired chemical, physical, and electrical properties of the second material, or the desired chemical, physical, and electrical properties of the first material. Thus, by modifying the second polishing rate of the second material, the difference in polishing rates between the first material and the second material is reduced, and the deleterious tapers in the top surface, which are caused at least in part by over polishing a surface that has regions of different materials that have different polishing rates, tend to be eliminated or dramatically reduced, depending at least in part upon how closely the second polishing rate is matched to the first polishing rate by the modification of the second material.

Planarization system

Gaseous reactants capable of depositing a thin film on a semiconductor substrate are introduced into a deposition zone of a deposition apparatus through a gaseous reactants dispersion apparatus having rounded corners and smoothed anodized surfaces and maintained at a temperature ranging from about 70.degree. C. to about 85.degree. C., and preferably from about 75.degree. C. to about 80.degree. C., to inhibit the deposition and accumulation on such surfaces of charged materials capable of generating particles which may cause damage to the semiconductor substrate.

Growing community of inventors

Fremont, CA, United States of America

Ming-Yi Lee